Logic Array Blocks and Adaptive Logic Modules User Guide: Agilex™ 3 FPGAs and SoCs
ID
846637
Date
4/07/2025
Public
2.1.2. Local and Direct Link Interconnects
Each LAB can drive out 60 ALM outputs. A subset of these outputs can directly drive LAB inputs. However, any connection to a different row or column must use at least one general-purpose routing wire.
The local interconnect drives the ALM inputs. ALM outputs, column interconnects, and row interconnects drive the local interconnect.
Figure 3. Agilex™ 3 LAB Local and Direct Link Interconnects