Logic Array Blocks and Adaptive Logic Modules User Guide: Agilex™ 3 FPGAs and SoCs
ID
846637
Date
4/07/2025
Public
2.1.4.1. Clear Logic Control
LAB-wide signals control the logic for the clear signal of the ALM register. The ALM register directly supports both a synchronous and an asynchronous clear. Each LAB supports one synchronous clear signal and two asynchronous clear signals.
Figure 5. Agilex™ 3 LAB-Wide Control Signals