Test Engine FPGA IP Release Notes: Agilex™ 3, Agilex™ 5, and Agilex™ 7 FPGAs

ID 837722
Date 7/07/2025
Public

1.3. Test Engine FPGA IP v2.0.0

Table 3.  v2.0.0 2025.01.13
Description Impact
Added Call simulation finish top-level parameter. The Call simulation finish function was enabled by default in previous versions. The addition of this Call simulation finish parameter provides you the flexibility to disable this function, if desired.
Added a new Memory Traversal helper function. The Memory Traversal helper function has been added to the MemAXI4DriverPrograms. HBM2E Traffic programs have been added as examples of its usage.
Note: This documentation is preliminary and subject to change.