Test Engine FPGA IP Release Notes: Agilex™ 3, Agilex™ 5, and Agilex™ 7 FPGAs

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ID 837722
Date 7/07/2025
Public

1.4. Test Engine FPGA IP v1.2.0

Table 4.  v1.2.0 2024.11.04
Description Impact
Enabled support to compile different programs for multiple drivers. You now have the option to select different traffic patterns for each driver. For more information, refer to Script Options in the Test Engine IP User Guide.
Enhanced Max Address & Write Data PWM Denominator calculator. The Max Address & Write Data PWM Denominator calculator has been adjusted from 8 to 64.
Note: This documentation is preliminary and subject to change.
Level Two Title