GTS JESD204B Intel® FPGA IP User Guide

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ID 832100
Date 4/16/2025
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Document Table of Contents
Document Table of Contents x
1. GTS JESD204B IP Quick Reference 2. About the GTS JESD204B Intel® FPGA IP 3. Getting Started 4. GTS JESD204B IP Functional Description 5. GTS JESD204B IP Deterministic Latency Implementation Guidelines 6. GTS JESD204B IP Debug Guidelines 7. Document Revision History for the GTS JESD204B Intel® FPGA IP User Guide
2. About the GTS JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. GTS JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. GTS JESD204B IP Design Considerations 3.8. GTS JESD204B Intel® FPGA IP Parameters 3.9. Analog Parameter Settings 3.10. GTS JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the GTS JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. GTS JESD204B IP Design Considerations x
3.7.1. Integrating the GTS JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Configuring the GTS Reset Sequencer Intel® FPGA IP
4. GTS JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Dual Simplex Support 4.4. Operation 4.5. Clocking Scheme 4.6. Reset Scheme 4.7. Signals 4.8. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.4. Operation x
4.4.1. Operating Modes 4.4.2. Scrambler/Descrambler 4.4.3. SYNC_N Signal 4.4.4. Link Reinitialization 4.4.5. Link Startup Sequence 4.4.6. Error Reporting Through SYNC_N Signal
4.4.1. Operating Modes x
4.4.1.1. Subclass 0 Operating Mode 4.4.1.2. Subclass 1 Operating Mode 4.4.1.3. Subclass 2 Operating Mode
4.5. Clocking Scheme x
4.5.1. Device Clock 4.5.2. Link Clock 4.5.3. Local MultiFrame Clock 4.5.4. Clock Correlation 4.5.5. GTS Reset Sequencer Intel® FPGA IP Clock
4.6. Reset Scheme x
4.6.1. Reset Sequence 4.6.2. TX Reset Entry and Exit Sequence 4.6.3. RX Reset Entry and Exit Sequence
4.7. Signals x
4.7.1. Transmitter Signals 4.7.2. Receiver Signals
4.8. Registers x
4.8.1. Register Access Type Convention 4.8.2. Register Map and Definition 4.8.3. Transmitter Registers 4.8.4. Receiver Registers
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. GTS JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. GTS JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Transceiver Toolkit
1. GTS JESD204B IP Quick Reference
2. About the GTS JESD204B Intel® FPGA IP
3. Getting Started
4. GTS JESD204B IP Functional Description
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines
6. GTS JESD204B IP Debug Guidelines
7. Document Revision History for the GTS JESD204B Intel® FPGA IP User Guide

4.6. Reset Scheme

All resets in the GTS JESD204B IP are synchronous reset signals and should be asserted and deasserted synchronously.
Note: Ensure that the resets are synchronized to the respective clocks for reset assertion and deassertion.
Table 17.   GTS JESD204B IP Resets
Reset Signal Associated Clock Description

jesd204_tx_avs_rst_n

jesd204_rx_avs_rst_n

jesd204_tx_avs_clk

jesd204_rx_avs_clk

This reset is associated with the jesd204_tx_avs_clk signal. This reset is an active low signal. You can assert this reset signal asynchronously but must deassert it synchronously to the jesd204_tx_avs_clk signal. After you deassert this signal, the CPU can configure the CSRs.

This reset is associated with the jesd204_rx_avs_clk signal. This reset is an active low signal. You can assert this reset signal asynchronously but must deassert it synchronously to the jesd204_rx_avs_clk signal. After you deassert this signal, the CPU can configure the CSRs.

jesd204_tx_rst_n

jesd204_rx_rst_n

Asynchronous

From User. Async Assertion and Deassertion.

Assertion triggers reset sequence to MAC and PHY. Reset sequence completion indicated by assertion tx_rst_ack_n.

Deassertion triggers out-of-reset sequence. Out of reset completion indicates by deassertion of tx_rst_ack_n.

User is required to assert this reset if tx_avs_rst_n is asserted.

Assertion triggers reset sequence to MAC and PHY. Reset sequence completion indicated by assertion rx_rst_ack_n.

Deassertion triggers out-of-reset sequence. Out of reset completion indicates by deassertion of rx_rst_ack_n.

User is required to assert this reset if rx_avs_rst_n is asserted.

jesd204_tx_rst_ack_n

jesd204_rx_rst_ack_n

Asynchronous

To User. To indicate the transceiver is fully in reset. Async Assertion and Deassertion.

(IP uses avs_clk or reconfig_xcvr_clk internally)

jesd204_tx_out_of_reset

jesd204_rx_out_of_reset

Asynchronous

To indicate the reset status of the SIP link layer. Async Assertion and Deassertion.

(IP uses avs_clk or reconfig_xcvr_clk internally)

User may optionally observe jesd204_tx_out_of_reset = 1 to indicate SIP out of reset to pulse SYSREF for subclass 1. User must synchronize this signal before use.

User may optionally observe jesd204_rx_out_of_reset = 1 to indicate SIP out of reset to pulse SYSREF for subclass 1. User must synchronize this signal before use.

0: SIP in reset

1: SIP out of reset

reconfig_xcvr_reset

jesd204_tx_avs_clk

jesd204_rx_avs_clk

From User: XCVR reconfiguration reset.

Active High. During duplex mode, both TX and RX share the same reconfig pins.

User is recommended to tie this to tx_avs_rst_n.

Section Content
Reset Sequence
TX Reset Entry and Exit Sequence
RX Reset Entry and Exit Sequence

Level Two Title