GTS JESD204B Intel® FPGA IP User Guide

Download PDF
ID 832100
Date 4/16/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS JESD204B IP Quick Reference 2. About the GTS JESD204B Intel® FPGA IP 3. Getting Started 4. GTS JESD204B IP Functional Description 5. GTS JESD204B IP Deterministic Latency Implementation Guidelines 6. GTS JESD204B IP Debug Guidelines 7. Document Revision History for the GTS JESD204B Intel® FPGA IP User Guide
2. About the GTS JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. GTS JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. GTS JESD204B IP Design Considerations 3.8. GTS JESD204B Intel® FPGA IP Parameters 3.9. Analog Parameter Settings 3.10. GTS JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the GTS JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. GTS JESD204B IP Design Considerations x
3.7.1. Integrating the GTS JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Configuring the GTS Reset Sequencer Intel® FPGA IP
4. GTS JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Dual Simplex Support 4.4. Operation 4.5. Clocking Scheme 4.6. Reset Scheme 4.7. Signals 4.8. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.4. Operation x
4.4.1. Operating Modes 4.4.2. Scrambler/Descrambler 4.4.3. SYNC_N Signal 4.4.4. Link Reinitialization 4.4.5. Link Startup Sequence 4.4.6. Error Reporting Through SYNC_N Signal
4.4.1. Operating Modes x
4.4.1.1. Subclass 0 Operating Mode 4.4.1.2. Subclass 1 Operating Mode 4.4.1.3. Subclass 2 Operating Mode
4.5. Clocking Scheme x
4.5.1. Device Clock 4.5.2. Link Clock 4.5.3. Local MultiFrame Clock 4.5.4. Clock Correlation 4.5.5. GTS Reset Sequencer Intel® FPGA IP Clock
4.6. Reset Scheme x
4.6.1. Reset Sequence 4.6.2. TX Reset Entry and Exit Sequence 4.6.3. RX Reset Entry and Exit Sequence
4.7. Signals x
4.7.1. Transmitter Signals 4.7.2. Receiver Signals
4.8. Registers x
4.8.1. Register Access Type Convention 4.8.2. Register Map and Definition 4.8.3. Transmitter Registers 4.8.4. Receiver Registers
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. GTS JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. GTS JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Transceiver Toolkit
1. GTS JESD204B IP Quick Reference
2. About the GTS JESD204B Intel® FPGA IP
3. Getting Started
4. GTS JESD204B IP Functional Description
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines
6. GTS JESD204B IP Debug Guidelines
7. Document Revision History for the GTS JESD204B Intel® FPGA IP User Guide

3.6.2. Parameterizing and Generating the IP

Refer to GTS JESD204B Intel FPGA IP Parameters for the IP core parameter values and description.

  1. In the IP Catalog (Tools > IP Catalog), locate and double-click the GTS JESD204B Intel® FPGA IP.
  2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target Intel® FPGA device family and output file HDL preference. Click OK.
  3. In the Main tab, set the following options:
    • Device family
    • JESD204b wrapper
    • Data path
    • JESD204b subclass
    • Data Rate
    • PLL/CDR Reference Clock Frequency
    • PCS Option
    • Enable Bit reversal and Byte reversal
    • Enable PMA Avalon memory-mapped interface
    • Enable Native PHY Debug Master Endpoint 4
    • Enable control and status registers
  4. In the JESD204b Configurations tab, select the following configurations:
    • Common configurations (L, M, Enable manual F configuration, F, N, N', S, K)
    • Advanced configurations (SCR, CS, CF, HD, ECC_EN, TX_EFIFO_PIPE_EN, PHADJ, ADJCNT, ADJDIR)
  5. In the Configurations and Status Registers tab, set the following configurations:
    • Device ID
    • Bank ID
    • Lane ID
    • Lane checksum
  6. After parameterizing the core, go to the Example Design tab and click Generate Example Design to create the simulation testbench. Skip to 8 if you do not want to generate the design example.
  7. In the Analog Parameters tab, select the following configurations:
    • Analog TX (Spread Spectrum, Enable TX P&N Invert, TX EQ Post Tap 1, TX EQ Main Tap, TX EQ Pre Tap 1, and TX EQ Pre Tap 2)
    • Analog RX (RX Adaptation mode, Enable TX P&N Invert, RX External Coupling Mode, Selects value of RX termination mode, Selects value of RX on-chip termination, and Enable VSR mode)
  8. Set a name for your <example_design_directory> and click OK to generate supporting files and scripts.
    The testbench and scripts are located in the <example_design_directory>.

    The Generate Example Design option generates supporting files for the following entities:

    • IP core design example for simulation—refer to Generating and Simulating the Design Example section in the respective design example user guides.
    • IP core design example for synthesis—refer to Compiling the GTS JESD204B IP Core Design Example section in the respective design example user guides.
  9. Click Finish or Generate HDL to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level .ip, .qip or .qsys IP variation file and HDL files for synthesis and simulation.

    The top-level IP variation is added to the current Quartus® Prime project. Click Project > Add/Remove Files in Project to manually add a .qip or .qsys file to a project. Make appropriate pin assignments to connect ports.

Note: Some parameter options are grayed out if they are not supported in a selected configuration or it is a derived parameter.
4 This parameter is optional and required only if system console access vis jtag is required.
Level Two Title