GTS JESD204B Intel® FPGA IP User Guide

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ID 832100
Date 4/16/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS JESD204B IP Quick Reference 2. About the GTS JESD204B Intel® FPGA IP 3. Getting Started 4. GTS JESD204B IP Functional Description 5. GTS JESD204B IP Deterministic Latency Implementation Guidelines 6. GTS JESD204B IP Debug Guidelines 7. Document Revision History for the GTS JESD204B Intel® FPGA IP User Guide
2. About the GTS JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. GTS JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. GTS JESD204B IP Design Considerations 3.8. GTS JESD204B Intel® FPGA IP Parameters 3.9. Analog Parameter Settings 3.10. GTS JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the GTS JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. GTS JESD204B IP Design Considerations x
3.7.1. Integrating the GTS JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Configuring the GTS Reset Sequencer Intel® FPGA IP
4. GTS JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Dual Simplex Support 4.4. Operation 4.5. Clocking Scheme 4.6. Reset Scheme 4.7. Signals 4.8. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.4. Operation x
4.4.1. Operating Modes 4.4.2. Scrambler/Descrambler 4.4.3. SYNC_N Signal 4.4.4. Link Reinitialization 4.4.5. Link Startup Sequence 4.4.6. Error Reporting Through SYNC_N Signal
4.4.1. Operating Modes x
4.4.1.1. Subclass 0 Operating Mode 4.4.1.2. Subclass 1 Operating Mode 4.4.1.3. Subclass 2 Operating Mode
4.5. Clocking Scheme x
4.5.1. Device Clock 4.5.2. Link Clock 4.5.3. Local MultiFrame Clock 4.5.4. Clock Correlation 4.5.5. GTS Reset Sequencer Intel® FPGA IP Clock
4.6. Reset Scheme x
4.6.1. Reset Sequence 4.6.2. TX Reset Entry and Exit Sequence 4.6.3. RX Reset Entry and Exit Sequence
4.7. Signals x
4.7.1. Transmitter Signals 4.7.2. Receiver Signals
4.8. Registers x
4.8.1. Register Access Type Convention 4.8.2. Register Map and Definition 4.8.3. Transmitter Registers 4.8.4. Receiver Registers
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. GTS JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. GTS JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Transceiver Toolkit
1. GTS JESD204B IP Quick Reference
2. About the GTS JESD204B Intel® FPGA IP
3. Getting Started
4. GTS JESD204B IP Functional Description
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines
6. GTS JESD204B IP Debug Guidelines
7. Document Revision History for the GTS JESD204B Intel® FPGA IP User Guide

3.8. GTS JESD204B Intel® FPGA IP Parameters

Table 11.   GTS JESD204B Intel® FPGA IP Parameters
Parameter Value Description
Main Tab
Device Family
  • Agilex™ 5
  • Agilex™ 3
The targeted device family.
JESD204B Wrapper
  • Base only
  • PHY only
  • Both Base and PHY

Select the JESD204B wrapper.

Base Only—generates the DLL only.

PHY Only—generates the transceiver PHY layer only (soft and hard PCS).

Both Base and PHY—generates both DLL and transceiver PHY layers.

Data Path
  • Receiver
  • Transmitter
  • Duplex

Select the operation modes. This selection enables or disables the receiver and transmitter supporting logic.

  • RX—instantiates the receiver to interface to the ADC.
  • TX—instantiates the transmitter to interface to the DAC.
  • Duplex—instantiates the receiver and transmitter to interface to both the ADC and DAC.
JESD204B Subclass
  • 0
  • 1
  • 2

Select the GTS JESD204B subclass modes.

  • 0—Set subclass 0
  • 1—Set subclass 1
  • 2—Set subclass 2
i.e.:
  • 1—Set subclass 1 (SYSREF)
  • 2—Set subclass 2 (SYNC_N)
Data Rate
  • 2.0–19.66
  • 2.0–12.50

Set the data rate for each lane.

  • Agilex™ 5—2.0 Gbps to 19.66 Gbps
  • Agilex™ 3—2.0 Gbps to 12.50 Gbps
Note: The maximum data rate is limited due to different device speed grades, transceiver PMA speed grades, and PCS options. Refer to Performance and Resource Utilization for the maximum data rate support.
PLL/CDR Reference Clock Frequency

Variable

Set the transceiver reference clock frequency for PLL or CDR.
PCS Option
  • Enabled Soft PCS

Supports Soft PCS mode only.

  • Enabled Soft PCS—use Soft PCS components for 8b10b encoder/decoder and word aligner.

Enable Bit reversal and Byte reversal

On, Off

The GTS JESD204B IP uses four 10-bit symbols (denoted as symbol3, symbol2, symbol1, and symbol0) for the 8b/10b encoding scheme. Symbol0 is the first symbol to be shifted out through the serial link while symbol3 is the last symbol to be shifted out.

  • Turn on this option to set the data transmission order to start from the least significant bit (lsb) of each symbol. For example, symbol0[0] is shifted out first, followed by symbol0[1], and so on until the entire symbol0 is shifted out. The transmission continues with symbol1[0] through symbol3[9].
  • Turn off this option to set the data transmission order to start from the most significant bit (msb) of each symbol. For example, symbol0[9] is shifted out first, followed by symbol0[8], and so on until the entire symbol0 is shifted out. The transmission continues with symbol1[9] through symbol3[0].
Enable PMA Avalon® memory-mapped interface On, Off Turn on this option for Avalon® memory-mapped interface in order to access transceiver PMA registers.
Enable Native PHY Debug Master Endpoint On, Off Turn this option on to include an embedded Native PHY Debug Master Endpoint in your JESD204B IP. The Native PHY Debug Master Endpoint can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option may require that a jtag_debug link be included in the system.
Enable Control and Status registers On, Off This option enables soft registers for reading status signals and writing control signals on the PHY interface through the embedded debug.
JESD204B Configurations Tab

Lanes per converter device (L)

  • Agilex™ 5: 1, 2, 4, 6, 8
  • Agilex™ 3: 1, 2, 4

Set the number of lanes per converter device.

Note: Refer to Performance and Resource Utilization for the common supported range for L and the resource utilization.

Converters per device (M)

1–256

Set the number of converters per converter device.

Enable manual F configuration On, Off

Turn on this option to set parameter F in manual mode and enable this parameter to be configurable. Otherwise, the parameter F is in derived mode.

You have to enable this parameter and configure the appropriate F value if the transport layer in your design is supporting Control Word (CF) or High Density format(HD), or both.

Note: The auto derived F value using formula F=M*S*N\'/(8*L) may not apply if parameter CF or parameter HD, or both are enabled.

Octets per frame (F)

1–256

The number of octets per frame is derived from F= M*N'*S/(8*L).

Converter resolution (N)

1–32

Set the number of conversion bits per converter.

Transmitted bits per sample (N')

4–32

Set the number of transmitted bits per sample (JESD204 word size, which is in nibble group).

Note: If parameter CF equals to 0 (no control word), parameter N' must be larger than or equal to sum of parameter N and parameter CS (N' ≥ N + CS). Otherwise, parameter N' must be larger than or equal to parameter N (N'≥N).

Frames per multiframe (K)

1–32
Set the number of frames per multiframe. This value is dependent on the value of F and is derived using the following constraints:
  • The value of K must fall within the range of 17/F <= K <= min(32, floor (1024/F))
  • The value of F*K must be divisible by 4

Samples per converter per frame (S)

1–32

Set the number of transmitted samples per converter per frame.

Enable scramble (SCR)

On, Off

Turn on this option to scramble the transmitted data or descramble the receiving data.

Control Bits (CS)

0–3

Set the number of control bits per conversion sample.

Control Words (CF)

0–32

Set the number of control words per frame clock period per link.

High density user data format (HD)

On, Off

Turn on this option to set the data format. This parameter controls whether a sample may be divided over more lanes.

  • On: High Density format
  • Off: Data should not cross the lane boundary

Enable Error Code Correction (ECC_EN)

On, Off

Turn on this option to enable error code correction (ECC) for memory blocks.

Phase adjustment request (PHADJ)

On, Off

Turn on this option to specify the phase adjustment request to the DAC.

  • On: Request for phase adjustment
  • Off: No phase adjustment

This parameter is valid for Subclass 2 mode only.

Adjustment resolution step count (ADJCNT) 0–15

Set the adjustment resolution for the DAC LMFC.

This parameter is valid for Subclass 2 mode only.

Direction of adjustment (ADJDIR)
  • Advance
  • Delay

Select to adjust the DAC LMFC direction.

This parameter is valid for Subclass 2 mode only.

Configurations and Status Registers Tab

Device ID

0–255

Set the device ID number.

Bank ID

0–15

Set the device bank ID number.

Lane# ID

0–31

Set the lane ID number.

Lane# checksum

0–255

Set the checksum for each lane ID.

Related Information
Level Two Title