DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs
2.2. DisplayPort IP Design Example Clock Domains
| Clock in diagram | Description |
|---|---|
| SysPLL refclk | The GTS System PLL can reference any clock frequency that the System PLL can divide to produce the desired output frequency. In this design example, system_pll_clk_link and rx/tx refclk_link share the same 150 MHz refclk. It must be a free running clock which is connected from a dedicated transceiver reference clock pin to the input clock port of System PLL Clocks IP, before connecting the corresponding output port to DisplayPort PHY Top. |
| Transceiver Refclk | The GTS PMA reference clocks must come from a free-running 150 MHz refclk pin. The PMA generates all supported DisplayPort line rates from this clock. This clock pin may be shared with the SystemPLL when enabled. |
| system_pll_clk_link | The minimum System PLL output frequency to support all DisplayPort rates up to UHBR13.5 is 421.9 MHz. This design example uses a 700 MHz (highest) output frequency so that SysPLL refclk can be shared with rx/tx refclk_link, which is 150 MHz. |
| rx_cdr_refclk_link and tx_pll_refclk_link | RX CDR and TX PLL Link refclk. Fixed to 150 MHz to support all DisplayPort data rates. |
| rx_ls_clkout and tx_ls_clkout | DisplayPort Link Speed Clock to clock DisplayPort IP. The frequency is equivalent to Data Rate divided by parallel data width. Example: Frequency = data rate / data width For HBR3:
For UHBR10:
For UHBR13.5:
|