2.6. Design Limitations and Known Issues

GTS SDI II IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 823543

Date 9/30/2025

Version

Public

Document Table of Contents

Document Table of Contents x

1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

1. GTS SDI II IP Design Example Quick Start Guide x

1.1. SDI II Design Example Directory Structure 1.2. Generating a GTS SDI II Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters

1.4. Compiling and Testing the SDI II Design Example in Hardware x

1.4.1. Testing in Hardware - Parallel or Serial Loopback

2. Design Example Detailed Description x

2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Design Limitations and Known Issues

2.3. Functional Description x

2.3.1. Design Components 2.3.2. Clocking Scheme

2.3.2. Clocking Scheme x

2.3.2.1. Clocking Scheme Components

2.4. Simulation x

2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description

1. GTS SDI II IP Design Example Quick Start Guide

1.1. SDI II Design Example Directory Structure

1.2. Generating a GTS SDI II Design

1.3. Compiling and Simulating the Design

1.4. Compiling and Testing the SDI II Design Example in Hardware

1.4.1. Testing in Hardware - Parallel or Serial Loopback

1.5. SDI II Design Example Parameters

2. Design Example Detailed Description

2.1. Features

2.2. Hardware and Software Requirements

2.3. Functional Description

2.3.1. Design Components

2.3.2. Clocking Scheme

2.3.2.1. Clocking Scheme Components

2.4. Simulation

2.4.1. SDI II Design Example Testbench Components

2.4.2. Test Description

2.5. SDI II Design Example Signals

2.6. Design Limitations and Known Issues

Design Limitations
Known Issues

3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives

4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.6. Design Limitations and Known Issues

For the GTS SDI IP Design Example.

Design Limitations

The GTS SDI II IP Design Example has the following lmitation:

The device package with a single quad example for Agilex 3 devices supports only serial loopback design, because of a limitation on the number of reference transceiver clocks in the transceiver bank. For VCXO and VCXO-less designs, three reference clocks are required.