Scalable Scatter-Gather DMA FPGA IP Design Example User Guide

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ID 823179
Date 9/22/2025
Public
Document Table of Contents
Document Table of Contents x
1. Product Discontinuance Notification 2. Design Example Description 3. Quick Start Guide 4. Document Revision History for the Scalable Scatter-Gather DMA FPGA IP Design Example User Guide
2. Design Example Description x
2.1. H2D ST to D2H ST Loopback Design Example
2.1. H2D ST to D2H ST Loopback Design Example x
2.1.1. DMA PCIe* Mode Design Example 2.1.2. DMA SoC Mode Design Example
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Testbench 3.5. Compiling the Design Example 3.6. Hardware and Software Requirements 3.7. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. DMA SoC Mode Example Design 3.3.2. DMA PCIe Mode Example Design
3.3.2. DMA PCIe Mode Example Design x
3.3.2.1. Running Simulation using VCS* MX 3.3.2.2. Running Simulation Using QuestaSim* 3.3.2.3. Running Simulation using Xcelium 3.3.2.4. Running Simulation using Riviera-PRO
3.4. Testbench x
3.4.1. DMA SoC Mode H2D ST to D2H ST Loopback Example Testbench 3.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench
3.4.2. DMA PCIe Mode H2D ST to D2H ST Loopback & H2D MM Example Testbench x
3.4.2.1. Design Example Testbench
3.7. Running the Design Example x
3.7.1. Running the DMA SoC Mode H2D ST to D2H ST Loopback Design Example 3.7.2. Running the DMA PCIe Mode H2D ST to D2H ST Loopback Design Example
3.7.1. Running the DMA SoC Mode H2D ST to D2H ST Loopback Design Example x
3.7.1.1. Building the Software Application Project for Nios® V/m Processor 3.7.1.2. Programming the Example Design into the Development Board
3.7.2. Running the DMA PCIe Mode H2D ST to D2H ST Loopback Design Example x
3.7.2.1. Installing the Linux Kernel Driver 3.7.2.2. Running the Loopback Design Example
3.7.2.2. Running the Loopback Design Example x
3.7.2.2.1. Testing H2D ST to D2H ST Loopback 3.7.2.2.2. Testing H2D MM
1. Product Discontinuance Notification
2. Design Example Description
3. Quick Start Guide
4. Document Revision History for the Scalable Scatter-Gather DMA FPGA IP Design Example User Guide

1. Product Discontinuance Notification

Updated for:
Intel® Quartus® Prime Design Suite 25.1.1
IP Version 1.2.0
Attention:

The Scalable Scatter-Gather DMA FPGA IP is part of a product obsolescence and support discontinuation schedule.

For new designs, Altera® recommends that you use other IPs with equivalent functions. To see a list of available IPs, refer to the Altera® FPGA IP Portfolio web page.

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