JTAG Boundary-Scan Testing User Guide: Agilex™ 5 FPGAs and SoCs
ID
820038
Date
4/01/2024
Public
1. Agilex™ 5 JTAG BST Overview
2. Agilex™ 5 JTAG BST Architecture
3. Agilex™ 5 BST Operation Control
4. Agilex™ 5 I/O Voltage for JTAG Operation
5. Enabling and Disabling Agilex™ 5 BST Circuitry
6. Agilex™ 5 BST Guidelines
7. Document Revision History for the JTAG Boundary-Scan Testing User Guide: Agilex™ 5 FPGAs and SoCs
5.1. Enabling BST Circuitry
The IEEE Std. 1149.1 BST circuitry is enabled after the device is configured. If you need to perform the boundary-scan test prior to configuration, you must execute the MISCCTRL instruction upon device power up to enable the BST circuitry.
MISCCTRL Instruction for Agilex™ 5 Devices
!Shift 10-bit MISCCTRL instruction (0x013) to Instruction Register SIR 10 TDI (013); !Transition to Run-Test-Idle state STATE IDLE; !Shift 8-bit data (0x01) to Data Register for BST circuitry enabling SDR 8 TDI (01);