JTAG Boundary-Scan Testing User Guide: Agilex™ 5 FPGAs and SoCs

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ID 820038
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 JTAG BST Overview 2. Agilex™ 5 JTAG BST Architecture 3. Agilex™ 5 BST Operation Control 4. Agilex™ 5 I/O Voltage for JTAG Operation 5. Enabling and Disabling Agilex™ 5 BST Circuitry 6. Agilex™ 5 BST Guidelines 7. Document Revision History for the JTAG Boundary-Scan Testing User Guide: Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 JTAG BST Architecture x
2.1. JTAG Circuitry Functional Model 2.2. JTAG Pins 2.3. IEEE Std. 1149.1 Boundary-Scan Register 2.4. IEEE Std. 1149.6 Boundary-Scan Register
2.3. IEEE Std. 1149.1 Boundary-Scan Register x
2.3.1. Boundary-Scan Cells of Agilex™ 5 Device I/O Pin
3. Agilex™ 5 BST Operation Control x
3.1. Device ID 3.2. Supported JTAG Instructions
5. Enabling and Disabling Agilex™ 5 BST Circuitry x
5.1. Enabling BST Circuitry 5.2. Disabling BST Circuitry
6. Agilex™ 5 BST Guidelines x
6.1. Performing Agilex™ 5 Boundary-Scan Testing 6.2. Agilex™ 5 IEEE Std. 1149.1 BST Guidelines
1. Agilex™ 5 JTAG BST Overview
2. Agilex™ 5 JTAG BST Architecture
3. Agilex™ 5 BST Operation Control
4. Agilex™ 5 I/O Voltage for JTAG Operation
5. Enabling and Disabling Agilex™ 5 BST Circuitry
6. Agilex™ 5 BST Guidelines
7. Document Revision History for the JTAG Boundary-Scan Testing User Guide: Agilex™ 5 FPGAs and SoCs

5.2. Disabling BST Circuitry

To ensure that you do not inadvertently enable the IEEE Std. 1149.1 circuitry when it is not required, disable the circuitry permanently with pin connections as listed in the following table.

Table 6.  Pin Connections to Permanently Disable the IEEE Std. 1149.1 Circuitry for Agilex™ 5 Devices
JTAG Pins4 Connection for Disabling
TMS VCCIO_SDM
TCK GND
TDI VCCIO_SDM
TDO Leave open
4 The JTAG pins are dedicated. Software option is not available to disable JTAG in Agilex™ 5 devices.
Level Two Title