JTAG Boundary-Scan Testing User Guide: Agilex™ 5 FPGAs and SoCs

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ID 820038
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 JTAG BST Overview 2. Agilex™ 5 JTAG BST Architecture 3. Agilex™ 5 BST Operation Control 4. Agilex™ 5 I/O Voltage for JTAG Operation 5. Enabling and Disabling Agilex™ 5 BST Circuitry 6. Agilex™ 5 BST Guidelines 7. Document Revision History for the JTAG Boundary-Scan Testing User Guide: Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 JTAG BST Architecture x
2.1. JTAG Circuitry Functional Model 2.2. JTAG Pins 2.3. IEEE Std. 1149.1 Boundary-Scan Register 2.4. IEEE Std. 1149.6 Boundary-Scan Register
2.3. IEEE Std. 1149.1 Boundary-Scan Register x
2.3.1. Boundary-Scan Cells of Agilex™ 5 Device I/O Pin
3. Agilex™ 5 BST Operation Control x
3.1. Device ID 3.2. Supported JTAG Instructions
5. Enabling and Disabling Agilex™ 5 BST Circuitry x
5.1. Enabling BST Circuitry 5.2. Disabling BST Circuitry
6. Agilex™ 5 BST Guidelines x
6.1. Performing Agilex™ 5 Boundary-Scan Testing 6.2. Agilex™ 5 IEEE Std. 1149.1 BST Guidelines
1. Agilex™ 5 JTAG BST Overview
2. Agilex™ 5 JTAG BST Architecture
3. Agilex™ 5 BST Operation Control
4. Agilex™ 5 I/O Voltage for JTAG Operation
5. Enabling and Disabling Agilex™ 5 BST Circuitry
6. Agilex™ 5 BST Guidelines
7. Document Revision History for the JTAG Boundary-Scan Testing User Guide: Agilex™ 5 FPGAs and SoCs

1. Agilex™ 5 JTAG BST Overview

Agilex™ 5 devices support IEEE Std. 1149.1 BST and IEEE Std. 1149.6 BST. When you perform Boundary-Scan Test (BST), you can test pin connections without using physical test probes and capture functional data during normal operation. The boundary-scan cells (BSCs) in a device can force signals onto pins, or capture data from pin or core logic signals. Forced test data is serially shifted into the BSCs. Captured data is serially shifted out and externally compared to expected results.

Agilex™ 5 devices are implemented using Monolithic die architecture, providing higher system integration and lower power in smaller form factor packages. The die implementation is transparent to BST. There is a single boundary-scan chain for the complete device that includes every die inside the package.

You can perform BST on Agilex™ 5 devices before, after, and during configuration.

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