GTS Interlaken Intel® FPGA IP User Guide

ID 819200
Date 7/08/2024
Public

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5.6. GTS Interlaken IP Reconfiguration Signals

Table 30.  GTS Interlaken IP Reconfiguration Signals
Signal Name Width (Bits) I/O Direction Available In Description
reconfig_clk 1 Input Interlaken Mode Avalon memory-mapped reconfiguration clock
reconfig_reset 1 input Interlaken Mode Avalon memory-mapped reconfiguration reset synchronous to reconfig_clk
reconfig_read 1 input Interlaken Mode Avalon memory-mapped reconfiguration read Command
reconfig_write 1 input Interlaken Mode Avalon memory-mapped reconfiguration write Command
reconfig_address 18 + RECONF_ADDR input Interlaken Mode Avalon memory-mapped transceiver reconfiguration address . 18 bits for Avalon memory-mapped addressing. If lanes are 4; RECONF_ADDR = 2; else if lanes are 6: RECONF_ADDR = 3 else if lanes are 8: RECONF_ADDR =3
reconfig_readdata 32 output. Interlaken Mode Avalon memory-mapped XCVR reconfiguration read data
reconfig_readdatavalid 1 output Interlaken Mode Avalon memory-mapped XCVR reconfiguration read data valid
reconfig_waitrequest 1 Output Interlaken Mode Avalon memory-mapped XCVR reconfiguration wait request
reconfig_writedata 32 input Interlaken Mode Avalon memory-mapped reconfiguration write data
reconfig_byteenable 4 input Interlaken Mode Avalon memory-mapped reconfiguration byte enable