5.2. AXI4 Interface Signals
For information on AXI4 signals for the FPGA memory interface IPs that you may connect with the PMON IP, refer to the following documentation: External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide or External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs, as appropriate, or to the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide.
Port Name | Width | Direction | Description |
---|---|---|---|
sink_axi4_awregion | 4 | Input | Region identifier. Permits a single physical interface on a subordinate to be used for multiple logical interfaces. Optional port on the interface controlled by Use AWREGION parameter. |
sink_axi4_awready | 1 | Output | Write Address Channel Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals. |
sink_axi4_awvalid | 1 | Input | Write Address Channel Valid. This signal indicates that valid write address and control information are available. |
sink_axi4_awid | 1-18 | Input | Write address channel command ID tag. The width of this signal is determined by the Write ID Width parameter. |
sink_axi_awaddr | 1-64 | Input | Write address. The write address gives the address of the first transfer in a write burst transaction. The width is tied to the value of the Write Address Width parameter. |
sink_axi4_awlen | 8 | Input | Burst Length. The burst length gives the exact number of transfers in an AXI burst. |
sink_axi4_awsize | 3 | Input | Burst Size. This signal indicates the number of AXI byte lanes containing valid data in each transfer of the burst. |
sink_axi4_awburst | 2 | Input | Burst type. The burst type and length determine how the address for each transfer within the burst is calculated. |
sink_axi4_awqos | 4 | Input | Quality-of-service identifier for this write command. This signal is optional on the interface, and determined by the Use AWQOS parameter. |
sink_axi4_awlock | 1 | Input | Lock Type. Provides additional information about the atomic characteristics of the transfer. |
sink_axi4_awuser | 1-64 | Input | Optional User-defined signal in the write address channel. Width will match the AWUSER parameter. |
sink_axi4_awport | 3 | Input | Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. This is controlled by the Use AWPROT parameter. |
sink_axi4_awcache | 4 | Input | Memory type. This signal indicates how transactions are required to progress through a system. This is an optional port controlled by the Use AWCACHE parameter. |
Port Name | Width | Direction | Description |
---|---|---|---|
sink_axi4_wready | 1 | Output | Write Channel Ready. This signal indicates that the subordinate can accept the write data. |
sink_axi4_wvalid | 1 | Input | Write Channel Valid. This signal indicates that valid write data and strobes are available. |
sink_axi4_wuser | 1-64 | Input | User signal. Optional User-defined signal in the write data channel. Value is determined by the Write Data width parameter. If this value is 0 this port is not added to the interface. |
sink_axi4_wdata | 8, 16, 32, 64, 128, 256, 512, 1024 | Input | Write Data. The port width is equal to 2^N where N is a positive integer between 3 and 10, where N is equal to the floor of log2 of the Write Data Width parameter. |
sink_axi4_wstrb | 1, 2, 4, 8, 16, 32, 64, 128 | Input | Write Strobes (Byte Enables). The width of the wstrb port is equal to wdata port divided by 8. |
sink_axi4_wlast | 1 | Input | Write Last. This signal indicates the last transfer in a write burst. |
Port Name | Width | Direction | Description |
---|---|---|---|
sink_axi4_buser | 1-64 | Output | User signal. Optional User-defined signal in the write response channel. Optional signal on the interface controlled by Use BUSER and BUSER width Parameters. |
sink_axi4_bready | 1 | Input | Write Response Channel Ready. This signal indicates that the manager can accept a write response. |
sink_axi4_bvalid | 1 | Output | Write Response Channel Valid. This signal indicates that a valid write response is available. |
sink_axi4_bid | 1-64 | Output | Response ID Tag. This signal is the ID tag of the write response, and matches the ID tag of the command for which this is the response. Controlled by Write ID width parameter. |
sink_axi4_bresp | 2 | Output | Write Response. This signal indicates the result of the Write command. |
Port Name | Width | Direction | Description |
---|---|---|---|
sink_axi4_arregion | 4 | Input | Region identifier. Permits a single physical interface on a subordinate to be used for multiple logical interfaces Optional signal exposed if Use ARREGION parameter is set. |
sink_axi4_arready | 1 | Output | Read Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals. |
sink_axi4_arvalid | 1 | Input | Read Address Valid. This signal indicates that valid read address and control information are available. |
sink_axi4_arid | 1-18 | Input | Read address channel command ID tag. Controlled by the Read ID width parameter. |
sink_axi4_araddr | 1-64 | Input | Read Address. The read address gives the address of the first transfer in a read burst transaction. Controlled by Read Address Width Parameter and should have the same width range. |
sink_axi4_arlen | 8 | Input | Burst Length. The burst length gives the exact number of transfers in an AXI burst. |
sink_axi4_arsize | 3 | Input | Burst size. |
sink_axi4_arburst | 2 | Input | Burst type. The burst type and length determine how the address for each transfer within the burst is calculated. |
sink_axi4_arqos | 4 | Input | Quality-of-service identifier for this read command. This signal is optional and dependent on the Use ARQOS parameter. |
sink_axi4_arlock | 1 | Input | Lock type. This signal provides additional information about the atomic characteristics of the transfer. Optional signal on the interface exposed by Use ARLOCK. |
sink_axi4_aruser | 1-64 | Input | User signal. Optional User-defined signal in the read address channel. Optional signal controlled by Use ARUSER with width defined by the ARUSER WIDTH parameter. |
sink_axi4_arport | 3 | Input | Protection Type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. Optional signal on the interface set by the Use ARPROT parameter. |
sink_axi4_arcache | 4 | Input | Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access Optional signal controlled by Use ARCACHE. |
Port Name | Width | Direction | Description |
---|---|---|---|
sink_axi4_rresp | 2 | Output | Read response. This signal indicates the status of the read transfer. |
sink_axi4_rrready | 1 | Input | Read Response Channel Ready. This signal indicates that the manager can accept the read data and response information. |
sink_axi4_rvalid | 1 | Output | Read Valid. This signal indicates that a valid read response is available. |
sink_axi4_rid | 1-18 | Output | Read Response Channel Ready. This signal indicates that the manager can accept the read data and response information. The width range value is determined by the read id width. |
sink_axi4_rdata | 8, 16, 32, 64, 128, 256, 512, 1024 | Output | Read Data. The port width is equal to 2^N where N is a positive integer between 3 and 10, where N is equal to the floor of log2 of the Read Data Width parameter. |
sink_axi4_ruser | 1-64 | Output | User signal. Optional User-defined signal in the read data channel. Value is determined by Read Data width parameter - Read data width. If this value is 0 this port is not added to the interface. |
sink_axi4_rlast | 1 | Output | Read Last. This signal indicates the last transfer in a read burst. |
Port Name | Width | Direction | Description |
---|---|---|---|
src_axi4_awregion | 4 | Output | Region identifier. Permits a single physical interface on a subordinate to be used for multiple logical interfaces. Optional port on the interface controlled by Use AWREGION parameter. |
src_axi4_awready | 1 | Input | Write Address Channel Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals. |
src_axi4_awvalid | 1 | Output | Write Address Channel Valid. This signal indicates that valid write address and control information are available. |
src_axi4_awid | 1-18 | Output | Write address channel command ID tag. The width of this signal is determined by the Write ID Width parameter. |
src_axi_awaddr | 1-64 | Output | Write address. The write address gives the address of the first transfer in a write burst transaction. The width is tied to the value of the Write Address Width parameter. |
src_axi4_awlen | 8 | Output | Burst Length. The burst length gives the exact number of transfers in an AXI burst. |
src_axi4_awsize | 3 | Output | Burst Size. This signal indicates the number of AXI byte lanes containing valid data in each transfer of the burst. |
src_axi4_awburst | 2 | Output | Burst type. The burst type and length determine how the address for each transfer within the burst is calculated. |
src_axi4_awqos | 4 | Output | Quality-of-service identifier for this write command. This signal is optional on the interface, and determined by the Use AWQOS parameter. |
src_axi4_awlock | 1 | Output | Lock Type. Provides additional information about the atomic characteristics of the transfer. |
src_axi4_awuser | 1-64 | Output | Optional User-defined signal in the write address channel. Width will match the AWUSER parameter. |
src_axi4_awport | 3 | Output | Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. This is controlled by the Use AWPROT parameter. |
src_axi4_awcache | 4 | Output | Memory type. This signal indicates how transactions are required to progress through a system. This is an optional port controlled by the Use AWCACHE parameter. |
Port Name | Width | Direction | Description |
---|---|---|---|
src_axi4_wready | 1 | Input | Write Channel Ready. This signal indicates that the subordinate can accept the write data. |
src_axi4_wvalid | 1 | Output | Write Channel Valid. This signal indicates that valid write data and strobes are available. |
src_axi4_wuser | 1-64 | Output | User signal. Optional User-defined signal in the write data channel. Value is determined by the Write Data width parameter. If this value is 0 this port is not added to the interface. |
src_axi4_wdata | 8, 16, 32, 64, 128, 256, 512, 1024 | Output | Write Data. The port width is equal to 2^N where N is a positive integer between 3 and 10, where N is equal to the floor of log2 of the Write Data Width parameter. |
src_axi4_wstrb | 1, 2, 4, 8, 16, 32, 64, 128 | Output | Write Strobes (Byte Enables). The width of the wstrb port is equal to wdata port divided by 8. |
src_axi4_wlast | 1 | Output | Write Last. This signal indicates the last transfer in a write burst. |
Port Name | Width | Direction | Description |
---|---|---|---|
src_axi4_buser | 1-64 | Input | User signal. Optional User-defined signal in the write response channel. Optional signal on the interface controlled by Use BUSER and BUSER width Parameters. |
src_axi4_bready | 1 | Output | Write Response Channel Ready. This signal indicates that the manager can accept a write response. |
src_axi4_bvalid | 1 | Input | Write Response Channel Valid. This signal indicates that a valid write response is available. |
src_axi4_bid | 1-64 | Input | Response ID Tag. This signal is the ID tag of the write response, and matches the ID tag of the command for which this is the response. Controlled by Write ID width parameter. |
src_axi4_bresp | 2 | Input | Write Response. This signal indicates the result of the Write command. |
Port Name | Width | Direction | Description |
---|---|---|---|
src_axi4_arregion | 4 | Output | Region identifier. Permits a single physical interface on a subordinate to be used for multiple logical interfaces Optional signal exposed if Use ARREGION parameter is set. |
src_axi4_arready | 1 | Input | Read Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals. |
src_axi4_arvalid | 1 | Output | Read Address Valid. This signal indicates that valid read address and control information are available. |
src_axi4_arid | 1-18 | Output | Read address channel command ID tag. Controlled by the Read ID width parameter. |
src_axi4_araddr | 1-64 | Output | Read Address. The read address gives the address of the first transfer in a read burst transaction. Controlled by Read Address Width Parameter and should have the same width range. |
src_axi4_arlen | 8 | Output | Burst Length. The burst length gives the exact number of transfers in an AXI burst. |
src_axi4_arsize | 3 | Output | Burst size. |
src_axi4_arburst | 2 | Output | Burst type. The burst type and length determine how the address for each transfer within the burst is calculated. |
src_axi4_arqos | 4 | Output | Quality-of-service identifier for this read command. This signal is optional and dependent on the Use ARQOS parameter. |
src_axi4_arlock | 1 | Output | Lock type. This signal provides additional information about the atomic characteristics of the transfer. Optional signal on the interface exposed by Use ARLOCK. |
src_axi4_aruser | 1-64 | Output | User signal. Optional User-defined signal in the read address channel. Optional signal controlled by Use ARUSER with width defined by the ARUSER WIDTH parameter. |
src_axi4_arport | 3 | Output | Protection Type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. Optional signal on the interface set by the Use ARPROT parameter. |
src_axi4_arcache | 4 | Output | Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access Optional signal controlled by Use ARCACHE. |
Port Name | Width | Direction | Description |
---|---|---|---|
src_axi4_rresp | 2 | Input | Read response. This signal indicates the status of the read transfer. |
src_axi4_rrready | 1 | Output | Read Response Channel Ready. This signal indicates that the manager can accept the read data and response information. |
src_axi4_rvalid | 1 | Input | Read Valid. This signal indicates that a valid read response is available. |
src_axi4_rid | 1-18 | Input | Read Response Channel Ready. This signal indicates that the manager can accept the read data and response information. The width range value is determined by the read id width. |
src_axi4_rdata | 8, 16, 32, 64, 128, 256, 512, 1024 | Input | Read Data. The port width is equal to 2^N where N is a positive integer between 3 and 10, where N is equal to the floor of log2 of the Read Data Width parameter. |
src_axi4_ruser | 1-64 | Input | User signal. Optional User-defined signal in the read data channel. Value is determined by Read Data width parameter - Read data width. If this value is 0 this port is not added to the interface. |
src_axi4_rlast | 1 | Input | Read Last. This signal indicates the last transfer in a read burst. |