Test Engine FPGA IP User Guide: Agilex™ 3, Agilex™ 5, and Agilex™ 7 FPGAs

ID 817758
Date 3/31/2025
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.2.4. Memory Reset Driver Parameters

Figure 9. Group: Drivers / General

Table 10.  Group: Drivers / General
Display Name Description
Reset type Specifies the reset interface type of the memory IP. The supported value for this parameter is Memory Subsystem reset.