| 25.1.1 |
Updated the simulation model for the IP to enhance the simulation performance. |
The new simulation model allows you to achieve a faster simulation time. |
| Corrected the IP Parameter Editor settings for the Slot Clock Configuration, SR-IOV, Configuration Intercept Interface, and MSI-X parameters. |
No functional impact. |
| Corrected width of p<n>_ss_app_st_flrrcvd_tdata and p<n>_app_ss_st_flrcmpl_tdata signals starting from the IP release in the 24.3 version of the Quartus® Prime Pro Edition software. |
You may observe a compilation issue error due to signal width mismatch when migrating your design that uses the Function Reset Interface. Update the signal width in your design to resolve the error. |
| Rebranded IP name from GTS AXI Streaming Intel FPGA IP for PCI Express* to GTS AXI Streaming IP for PCI Express*. |
— |