| 24.3.1 |
Added new Hard IP modes for Agilex™ 5 5 D-Series FPGAs in the GTS AXI Streaming IP for PCI Express* to support bifurcation. |
Allows you to configure the PCIe* 4.0 x8 Hard IP to support bifurcation and perform early evaluation in the Quartus® Prime Pro Edition software. |
| Added new configuration options in the IP Parameter Editor for Active State Power Management support in the PCIe* 0/1 Power Management tab. |
Allows you to preconfigure the Active State Power Management support depending on your design requirements. |
| Added new configuration options in IP Parameter Editor for requested equalization for far-end TX preset vector in the PCIe* 0/1 Configuration, Debug and Extension Options tab. |
Provides you the option to change the TX equalization far-end preset vector from the recommended value for debug purposes. |
| Added the Gen4 x8 Interface 512-bit Endpoint PIO design example variant generation support for Agilex™ 5 D-Series FPGAs in the GTS AXI Streaming IP for PCI Express* . |
Allows you to perform early evaluation of the design example in simulation. |