| 25.1 |
Added Agilex™ 3 device family support. |
Allows you to implement the PCIe* interface using GTS AXI Streaming IP for PCI Express* in the Agilex™ 3 FPGAs and perform early evaluation in the Quartus® Prime Pro Edition software. |
| Added AXI-ST Sideband Header option in IP Parameter Editor. |
Provides an option for you to have separate header and data busses on the AXI-Stream interface instead of single data bus with the inline header option. |
| Introduced the Performance Design Example variant for the Agilex™ 5 device family. |
Allows you to evaluate the performance of the IP. Only simulation is supported in this release. |
| Added PCIe* 3.0 x4 PIO design example variant for Agilex™ 3 device family and PCIe* 3.0 x1 PIO design example variant for both the Agilex™ 3 and Agilex™ 5 device families. |
Allows you to evaluate the PCIe* 3.0 x4 and PCIe* 3.0 x1 IP variants in both simulation and hardware for the Agilex™ 5 device family. Only simulation is supported for the Agilex™ 3 device family. |