GTS AXI Streaming IP for PCI Express* Design Example User Guide
ID
817713
Date
8/04/2025
Public
A.1.1. ebfm_barwr Procedure
A.1.2. ebfm_barwr_imm Procedure
A.1.3. ebfm_barrd_wait Procedure
A.1.4. ebfm_barrd_nowt Procedure
A.1.5. ebfm_cfgwr_imm_wait Procedure
A.1.6. ebfm_cfgwr_imm_nowt Procedure
A.1.7. ebfm_cfgrd_wait Procedure
A.1.8. ebfm_cfgrd_nowt Procedure
A.1.9. BFM Configuration Procedures
A.1.10. BFM Shared Memory Access Procedures
A.1.11. BFM Log and Message Procedures
A.1.12. Verilog HDL Formatting Functions
1.2.3. On-Chip Memory (MEM)
An on-chip memory (MEM) component stores and reads data depending on the instructions from the PIO. The on-chip memory size is configured to 16 KB for the design example and supports memory address 0x0000 to 0x3FFF.