GTS AXI Streaming IP for PCI Express* Design Example User Guide
ID
817713
Date
8/04/2025
Public
A.1.1. ebfm_barwr Procedure
A.1.2. ebfm_barwr_imm Procedure
A.1.3. ebfm_barrd_wait Procedure
A.1.4. ebfm_barrd_nowt Procedure
A.1.5. ebfm_cfgwr_imm_wait Procedure
A.1.6. ebfm_cfgwr_imm_nowt Procedure
A.1.7. ebfm_cfgrd_wait Procedure
A.1.8. ebfm_cfgrd_nowt Procedure
A.1.9. BFM Configuration Procedures
A.1.10. BFM Shared Memory Access Procedures
A.1.11. BFM Log and Message Procedures
A.1.12. Verilog HDL Formatting Functions
A.1.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task
The ebfm_log_set_stop_on_msg_mask procedure controls which message types stop simulation. This procedure alters the default behavior of the simulation when errors occur as described in the BFM Log and Message Procedures.
Location |
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Syntax |
ebfm_log_set_stop_on_msg_mask(msg_mask) | |
Argument |
msg_mask | This argument is reg [EBFM_MSG_ERROR_CONTINUE:EBFM_MSG_DEBUG]. A 1 in a specific bit position of the msg_mask causes messages of the type corresponding to the bit position to stop the simulation after the message is displayed. |