GTS Transceiver PHY User Guide

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ID 817660
Date 10/07/2024
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Document Table of Contents
Document Table of Contents x
1. GTS Transceiver Overview 2. GTS Transceiver Architecture 3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP 4. Implementing the GTS System PLL Clocks Intel FPGA IP 5. Implementing the GTS Reset Sequencer Intel FPGA IP 6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 7. Design Assistance Tools 8. Debugging GTS Transceiver Links with Transceiver Toolkit 9. Document Revision History for the GTS Transceiver PHY User Guide
1. GTS Transceiver Overview x
1.1. GTS Transceiver Design Flow
2. GTS Transceiver Architecture x
2.1. Building Blocks 2.2. Channel Placement Rules and Design Requirements 2.3. PMA Architecture 2.4. PCS Architecture 2.5. Forward Error Correction (FEC) Architecture 2.6. Clock Architecture 2.7. Bonding and Deskew
2.1. Building Blocks x
2.1.1. PMA 2.1.2. FEC 2.1.3. PCS 2.1.4. Ethernet MAC 2.1.5. PCI Express* Hard IP 2.1.6. PLL and Clock Networks 2.1.7. Avalon® Memory-Mapped Interface
2.1.1. PMA x
2.1.1.1. Protocol Support Using PMA Direct Mode
2.1.1.1. Protocol Support Using PMA Direct Mode x
2.1.1.1.1. SDI 2.1.1.1.2. HDMI 2.1.1.1.3. DisplayPort 2.1.1.1.4. CPRI
2.2. Channel Placement Rules and Design Requirements x
2.2.1. Hard IP Rules 2.2.2. Use Scenario Rules 2.2.3. Unused PMA Rules 2.2.4. General Design Requirement
2.3. PMA Architecture x
2.3.1. Transmitter PMA Architecture 2.3.2. Receiver PMA Architecture 2.3.3. PMA Loopback Modes
2.3.1. Transmitter PMA Architecture x
2.3.1.1. Transmitter Buffer 2.3.1.2. Serializer 2.3.1.3. Data Pattern Generator and Verifier
2.3.2. Receiver PMA Architecture x
2.3.2.1. Receiver Buffer and Equalizer 2.3.2.2. Deserializer 2.3.2.3. CDR Block 2.3.2.4. PMA Tuning
2.3.2.1. Receiver Buffer and Equalizer x
2.3.2.1.1. Control Unit
2.5. Forward Error Correction (FEC) Architecture x
2.5.1. FEC Loopback Mode
2.6. Clock Architecture x
2.6.1. Reference Clock Network 2.6.2. Datapath Clock Network 2.6.3. System PLL 2.6.4. Datapath Clock Cadences 2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
2.6.1. Reference Clock Network x
2.6.1.1. Single GTS Transceiver Bank Device 2.6.1.2. PMA Primary PLL Configuration
2.6.3. System PLL x
2.6.3.1. I/O PLLs in HVIO Bank as System PLL 2.6.3.2. Running PCIe* and Non- PCIe* Protocols in a GTS Transceiver Bank 2.6.3.3. System PLL Clock for FPGA Core 2.6.3.4. System PLL with HVIO Reference Clock
2.7. Bonding and Deskew x
2.7.1. Bonding Architecture 2.7.2. TX Deskew Function
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.1. IP Overview 3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP 3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting reset 3.9. Bonding Implementation 3.10. Configuration Register 3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing 3.12. Configurable Quartus® Prime Software Settings 3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. PCS Direct Supported Modes 3.1.4. Unsupported PMA/FEC/PCS Modes
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.3.1. Preset IP Parameter Settings 3.3.2. Common Datapath Options 3.3.3. TX Datapath Options 3.3.4. RX Datapath Options 3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations 3.3.6. FEC Options 3.3.7. PCS Options 3.3.8. Avalon® Memory-Mapped Interface Options 3.3.9. Register Map IP-XACT Support 3.3.10. Analog Parameter Options
3.3.3. TX Datapath Options x
3.3.3.1. TX PMA Interface Parameters
3.3.4. RX Datapath Options x
3.3.4.1. RX PMA Interface Parameters
3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations x
3.3.5.1. PMA Configuration Rules for SDI Mode 3.3.5.2. PMA Configuration Rules for HDMI Mode 3.3.5.3. PMA Configuration Rules for DisplayPort Mode 3.3.5.4. PMA Configuration Rules for CPRI Mode
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. RX PMA Status Signals 3.4.7. TX and RX PMA and Core Interface FIFO Signals 3.4.8. Avalon Memory-Mapped Interface Signals
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. PMA Fractional Mode
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the i_tx_cadence_slow_clk_locked Port
3.8. Asserting reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Run-time Reset Sequence—TX 3.8.5. Run-time Reset Sequence—RX 3.8.6. Run-time Reset Sequence—TX + RX 3.8.7. RX Data Loss/CDR Lock Loss (Auto-Recovery) 3.8.8. TX PLL Lock Loss
3.9. Bonding Implementation x
3.9.1. Bonding Placement Requirements
3.10. Configuration Register x
3.10.1. GTS PMA and FEC Direct PHY Soft CSR Register Map 3.10.2. GTS PMA Register Map 3.10.3. Accessing Configuration Registers
3.10.2. GTS PMA Register Map x
3.10.2.1. Logical Avalon® Memory-Mapped Port Indexing
3.10.3. Accessing Configuration Registers x
3.10.3.1. Accessing GTS PMA and FEC Direct PHY Soft CSR Registers 3.10.3.2. Accessing GTS PMA Registers
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing x
3.11.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP 3.11.2. Using JTAG to Avalon Master Bridge Intel FPGA IP
3.11.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.11.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.11.2. Using JTAG to Avalon Master Bridge Intel FPGA IP x
3.11.2.1. RTL Connection Example for JTAG to Avalon Master Bridge Intel® FPGA IP
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.13.1. Direct Register Method 3.13.2. GTS Attribute Access Method
3.13.1. Direct Register Method x
3.13.1.1. Direct Register Method Examples
3.13.2. GTS Attribute Access Method x
3.13.2.1. GTS Attribute Access Method Example 1 3.13.2.2. GTS Attribute Access Method Example 2
4. Implementing the GTS System PLL Clocks Intel FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for GTS System PLL Clocks Intel FPGA IP Usage 4.5. Guidelines to Indicate System PLL Reference Clock is Ready
4.5. Guidelines to Indicate System PLL Reference Clock is Ready x
4.5.1. Example Flow to Indicate System PLL Reference Clock is Ready
5. Implementing the GTS Reset Sequencer Intel FPGA IP x
5.1. IP Requirements 5.2. IP Parameters 5.3. IP Port List 5.4. GTS Reset Sequencer Intel FPGA IP General Interface 5.5. GTS Reset Sequencer Intel FPGA IP Design Flow 5.6. GTS Reset Sequencer Intel FPGA IP Use Cases
5.6. GTS Reset Sequencer Intel FPGA IP Use Cases x
5.6.1. Example Use Case 1 5.6.2. Example Use Case 2
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP 6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description 6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench 6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.2.1. Fast Simulation Support 6.2.2. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Directory Structure
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench x
6.4.1. Modifying the Example Design and Performing Simulation
7. Design Assistance Tools x
7.1. Clocking and Datapath Tool 7.2. TX Equalizer Tool
8. Debugging GTS Transceiver Links with Transceiver Toolkit x
8.1. GTS Transceiver Toolkit Parameter Settings 8.2. GTS Transceiver Toolkit GUI 8.3. GTS Transceiver Debugging Flow Walkthrough
8.2. GTS Transceiver Toolkit GUI x
8.2.1. Collection View
8.3. GTS Transceiver Debugging Flow Walkthrough x
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit 8.3.2. Programming the Design into an Intel FPGA 8.3.3. Loading the Design to the Transceiver Toolkit 8.3.4. Creating Transceiver Links 8.3.5. Running BER Tests 8.3.6. Running Eye Viewer Tests 8.3.7. Running Link Optimization Tests
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide

9. Document Revision History for the GTS Transceiver PHY User Guide

Document Version Quartus® Prime Version Changes
2024.10.07 24.3 Made the following changes:
  • Corrected the Key GTS Transceiver Features table with the Ethernet Technology Consortium (ETC) FEC naming in the GTS Transceiver Overview chapter.
  • Added new figure GTS Transceiver Design Flow in the GTS Transceiver Overview chapter.
  • Added figure GTS Transceiver Bank Layout for E-Series FPGAs with 8 GTS Transceivers in the Building Blocks section.
  • Updated note about FEC support for PCS Direct mode in the Hard IP Configurations Supported with PMA table.
  • Added new section Protocol Support using PMA Direct Mode with sub-sections for SDI, HDMI, DisplayPort and CPRI protocol support information.
  • Updated the A5E 028 device power down support bank for the M16A package in the Selected E-Series GTS Transceiver Banks that Support Power Down table.
  • Updated the Data Pattern Generator and Verifier section with new information about the built-in PRBS generator and verifier.
  • Updated the PCS Architecture section with IEEE 802.3 compliant Clause 107 support and updated naming for the IEEE MII interface.
  • Corrected the Supported FEC Modes and Compliance Specifications table with the Ethernet Technology Consortium (ETC) FEC naming in the Forward Error Correction (FEC) Architecture section.
  • Added bonding support for the x6 and x8 modes for PCS Direct mode in the Bonding Architecture section.
  • Corrected the Ethernet Technology Consortium (ETC) FEC naming in the FEC Direct Supported Modes section.
  • Updated the PCS Direct Supported Modes section with simplex and duplex support and updated naming for the IEEE MII interface.
  • Updated supported modes in the Unsupported PMA/FEC/PCS Modes section.
  • Updated the Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP section with Riviera-PRO* simulator support.
  • Removed note from the Provide separate interface for each PMA parameter in the Common Datapath Options section.
  • Added new section PMA Configuration Rules for Specific Protocol Mode Implementation with sub-sections for PMA Configuration Rules for SDI Mode, PMA Configuration Rules for HDMI Mode, PMA Configuration Rules for DP Mode and PMA Configuration Rules for CPRI Mode protocol modes.
  • Corrected the Ethernet Technology Consortium (ETC) FEC naming in the FEC Options section.
  • Updated naming for the IEEE MII interface in the PCS Options section.
  • Removed note from the Enable separate Avalon interface per PMA parameter in the Avalon® Memory-Mapped Interface Options section.
  • Updated the Analog Parameter Options in Parameter Editor figure in the Analog Parameter Options section.
  • Removed signals o_tx_am_gen_start and i_tx_am_gen_2x_ack from the Reset Signals table.
  • Removed the PCS Direct Signals: IEEE and PCS Direct Signals: IEEE_FLEXE_66/PCS66 topics from the Signal and Port Reference section.
  • Added new tables TX and RX Parallel Data to IEEE MII Port Mapping Signals for PCS Direct Mode and TX and RX Parallel Data to IEEE_FLEXE_66/PCS66 Mapping Signals for PCS Direct Mode in the Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath section.
  • Removed signals o_tx_am_gen_start and i_tx_am_gen_2x_ack from the Reset Signal Requirements section.
  • Added note in the Run-time Reset Sequence—TX topic about RS-FEC mode support.
  • Removed the Run-time Reset Sequence—TX with FEC topic from the Reset Signal Requirements section.
  • Added note about using the TX Equalizer Tool in the TX Equalizer Co-efficients topic in the Direct Register Method Examples section.
  • Added Riviera-PRO* script location in the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Directory Structure section.
  • Added Riviera-PRO* script run command in the Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench section.
  • Added information about modifying the example design pin assignments in the Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design section.
2024.07.08 24.2 Made the following changes:
  • Added a note about restricted support for Agilex™ 5 D-Series FPGAs in the GTS Transceiver Overview section.
  • Updated the Agilex™ 5 D-Series FPGA package information in figures in the Building Blocks section.
  • Added new table with the Agilex™ 5 D-Series FPGA power down information in the Unused PMA Rules section.
  • Updated the System PLL Clock Network figure in the System PLL section.
  • Added new section Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank with information about shared clocking resources.
  • Clarified information in the I/O PLLs in HVIO Bank as System PLL section.
  • Added new section PCS Architecture with information about PCS direct modes.
  • Updated information in the FEC Loopback Mode section.
  • Added information about PCS direct mode in the Bonding Architecture section.
  • Updated the IP Overview section with the PCS direct mode information.
  • Updated the Preset IP Parameter Settings section with the PCS direct mode preset.
  • Updated PMA data rate parameter setting values and default value in description in the Common Datapath Options section.
  • Added new section PCS Options with information about the PCS direct parameter settings.
  • Updated the Enable readdatavalid port on Avalon® interface parameter setting in the Avalon® Memory-Mapped Interface Options section.
  • Added new section Register Map IP-XACT Support with information about the register map support in IP-XACT.
  • Added new section Analog Parameter Options with information about the RX and TX Analog parameter settings.
  • Added additional description for the i_tx_pll_refclk_p[N-1:0] and i_rx_cdr_refclk_p[N-1:0] signals in the TX and RX Reference Clock and Clock Output Interface Signals table.
  • Added PCS direct mode parallel data calculations in the Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath section.
  • Updated the RX Manual Tuning description in the Configurable Software Settings section.
  • Updated the register map addresses for TX equalization in Logical Avalon Memory-Mapped Port Indexing and Direct Register Method Examples sections.
  • Updated the GTS Attribute Access Data Value 1 table with TX to RX parallel loopback data field value.
  • Updated the GTS System PLL Clock Intel FPGA IP Parameters and Mode of System PLL - System PLL Reference Clock and Output Frequencies tables with PCIE_FREQ_500 value setting.
  • Updated the Guidelines for GTS System PLL Clocks Intel FPGA IP Usage section with PCIe* compliance information.
  • Updated the Implementing the GTS Reset Sequencer Intel FPGA IP chapter introduction.
  • Updated the GTS Reset Sequencer Intel FPGA IP Design Flow section with additional information.
  • Updated supported simulator from VCS* to VCS* MX in several sections.
  • Updated the Example Design Options table with PCS direct mode and several 28.1 Gbps options.
  • Updated the Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design section with development kit board selection information.
  • Updated the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description section with the PCS direct mode information.
  • Added note in the Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench section about VCS* MX waveform generation.
  • Added note in the Modifying the Example Design and Performing Simulation section about soft reset controller simulation model.
  • Added new section Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design.
  • Updated the Running Eye Viewer Tests section with information about the Eye Width measurements.
  • Updated the Running Link Optimization Tests section with information about the Eye Width measurements.
2024.04.01 24.1 Initial release.
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