F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide
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2.8. Design Example Interface Signals
The F-Tile Low Latency 50G Ethernet testbench is self-contained and does not require you to drive any input signals.
Signal | Direction | Comments |
---|---|---|
clk_ref | Input | This clocks the CDR in receive direction of the transceivers. Drive at 156.25 MHz. |
clk_status | Input | CSR clock |
i_clk_sys | Input | Input System PLL clock to F-Tile Low Latency 50G Ethernet Intel® FPGA IP. |
i_clk_ref | Input | Drive at 156.625 MHz. |
o_tx_serial[1:0] | Output | Transceiver PHY output serial data. |
i_rx_serial[1:0] | Input | Transceiver PHY input serial data. |