GTS CPRI PHY IP Design Example User Guide

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ID 814583
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS CPRI PHY Altera® FPGA IP Design Example User Guide Archives 4. Document History for GTS CPRI PHY Altera® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench
2. Design Example Description x
2.1. GTS CPRI PHY IP Design Example Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL 2.2.8. Reset Sequencer
1. Quick Start Guide
2. Design Example Description
3. GTS CPRI PHY Altera® FPGA IP Design Example User Guide Archives
4. Document History for GTS CPRI PHY Altera® FPGA IP Design Example User Guide

2.3. Simulation Design Example

The GTS CPRI PHY IP design example generates a simulation testbench and simulation files that instantiate the GTS CPRI PHY IP when you select the Simulation option.
Figure 6. Block Diagram for the Static Reconfiguration Design Example
Figure 7. Block Diagram for the Dynamic Reconfiguration Design ExampleThe system PLL frequency is eithe r 156.25 or 175 MHz (when you select 908.125 MHz as teh system PLL frequncy). The PHY reference clock is 184.32, 153.6, or 122.88 MHz.

In this design example, the simulation testbench provides basic functionality such as startup and wait for lock, transmit, and receive packets.

The successful test run displays output confirming the following behavior:
  1. The client logic resets the IP.
  2. The client logic waits for the RX datapath alignment.
  3. The client logic transmits hyperframes on the TX MII and waits for five hyperframes to be received on the RX MII. Hyperframes are transmitted and received on the MIIs, per the CPRI v7.0 specifications.
    Note: The CPRI designs that target 1.2, 2.4, 3, and 4.9 Gbps line rates use 8b/10b interface and the designs that target 10.1 Gbps (without RS-FEC) use MII.
    Note: This design example includes a round trip counter to count the round trip latency from TX to RX.
  4. The client logic reads the round trip latency value and checks for the content and correctness of the hyperframes data on the RX MII side once the counter completes the round trip latency count.
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