GTS CPRI PHY IP Design Example User Guide

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ID 814583
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS CPRI PHY Altera® FPGA IP Design Example User Guide Archives 4. Document History for GTS CPRI PHY Altera® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench
2. Design Example Description x
2.1. GTS CPRI PHY IP Design Example Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL 2.2.8. Reset Sequencer
1. Quick Start Guide
2. Design Example Description
3. GTS CPRI PHY Altera® FPGA IP Design Example User Guide Archives
4. Document History for GTS CPRI PHY Altera® FPGA IP Design Example User Guide

4. Document History for GTS CPRI PHY Altera® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2025.04.07 25.1 7.0.0
  • Added Dynamic reconfiguration parameter.
2024.01.13 24.3.1 6.0.0 Added support for the following line rates:
  • 10.1376 Gbps with RS-FEC
  • 12.16512 Gbps with RS-FEC
  • 24.33024 Gbps with RS-FEC
2024.10.07 24.3 5.0.0
  • Added support for 6.8G, 9G, 12G (without RS-FEC), and 24G (without RS-FEC)
  • Removed Synopsys VCS simulator
2024.03.31 24.1 3.0.0

Initial release.
Level Two Title