GTS CPRI PHY IP Design Example User Guide

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ID 814583
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS CPRI PHY Altera® FPGA IP Design Example User Guide Archives 4. Document History for GTS CPRI PHY Altera® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench
2. Design Example Description x
2.1. GTS CPRI PHY IP Design Example Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL 2.2.8. Reset Sequencer
1. Quick Start Guide
2. Design Example Description
3. GTS CPRI PHY Altera® FPGA IP Design Example User Guide Archives
4. Document History for GTS CPRI PHY Altera® FPGA IP Design Example User Guide

1.4. Simulating the Design Example Testbench

Figure 3. Procedure
Follow these steps to simulate the testbench:
  1. At the command prompt, change to the testbench simulation directory <design_example_dir>/example_testbench: 
    cd <my_design>/example_testbench
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
  3. Analyze the results. The successful testbench received five hyperframes, and displays "PASSED".
    Table 3.  Steps to Simulate the Testbench
    Simulator Instructions
    VCS* MX In the command line, type:
    sh run_vcsmx.sh
    QuestaSim* or Questa* Intel® FPGA Edition In the command line, type:
    vsim -do run_vsim.do
    If you prefer to simulate without bringing up the GUI, type: 
    vsim -c -do run_vsim.do
    Xcelium* In the command line, type:
    sh run_xcelium.sh

    The following sample output illustrates a successful simulation test run for 10.1376 Gbps with 1 CPRI channel:

    Figure 4. Simulation Output
    Figure 5. Simulation Output with Dynamic ReconfigurationThe following sample output shows a successfull simulation test run for dynamic reconfiguration with 9.8304 Gbps, 4.9152 Gbps, 3.072 Gbps, 2.4576 Gbps, 1.2288 Gbps CPRI.
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