Visible to Intel only — GUID: hvb1706644506339

Ixiasoft

Visible to Intel only — GUID: hvb1706644506339

Ixiasoft

## 6.3. Example 3: Known Cooling Capacity

_{CA}is a known value and can be entered in the PTC when you have selected a Calculation mode of Find available thermal margin for cooling solution.

This example assumes the same FPGA as in the previous examples. It is to be used in a design where the Ψ_{CA} is 2.8⁰ C/W.

By entering the ambient temperature and the known Ψ_{CA} value into the PTC, we can calculate the die thermal and power margins relative to the T_{J-MAX} of 100⁰ C. The figure below shows the results on the PTC Thermal tab. We can conclude that the power consumption of this FPGA can be increased by an additional 7 watts, while remaining within the limits of this cooling solution.

You can also use the following equation to calculate T_{J }once the thermal parameters are known:

T_{J}= T_{A}+ TDP * (Ѱ_{JC}+ Ѱ_{CA})

T_{J}= 50 + 10 * (0.5 + 2.8) = 78.5