GTS JESD204C Intel® FPGA IP Design Example User Guide

ID 813978
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

3.1. System Components

The GTS JESD204C design example provides a software-based control flow that uses the hard control unit with or without system console support.

The design example enables an auto link up in internal and external loopback modes.

You can either configure your own settings or use one of the two presets provided.

  • L=2, M=8, F=12, with data rate of 17.16 Gbps
  • L=4, M=8, F=4, with data rate of 16.22016 Gbps