GTS JESD204C Intel® FPGA IP Design Example User Guide

Download PDF
ID 813978
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide 2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204C Design Example 4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the GTS JESD204C Design Example x
3.1. System Components 3.2. GTS JESD204C Design Example Clock and Reset 3.3. GTS JESD204C Design Example Signals 3.4. GTS JESD204C Design Example Control Registers
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. Pattern Generator and Checker 3.1.9. GTS JESD204C TX and RX IP
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204C Design Example
4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide

2.4. Simulating the Design Example Testbench

The design example testbench simulates your generated design.
Figure 4. Procedure

To simulate the design, perform the following steps:

  1. Change the working directory to <example_design_directory> /simulation/<Simulator>.
  2. In the command line, run the simulation script. The table below shows the commands to run the supported simulators.
    Simulator Command
    QuestaSim* / ModelSim* vsim -do modelsim_sim.tcl
    vsim -c -do modelsim_sim.tcl (without QuestaSim* / ModelSim* GUI)
    VCS* sh vcs_sim.sh
    VCS* MX sh vcsmx_sim.sh
    The simulation ends with messages that indicate whether the run was successful or not.
    Figure 5. Successful SimulationThis figure shows the successful simulation message for VCS simulator.
Level Two Title