GTS JESD204C Intel® FPGA IP Design Example User Guide

Download PDF
ID 813978
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide 2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204C Design Example 4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the GTS JESD204C Design Example x
3.1. System Components 3.2. GTS JESD204C Design Example Clock and Reset 3.3. GTS JESD204C Design Example Signals 3.4. GTS JESD204C Design Example Control Registers
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. Pattern Generator and Checker 3.1.9. GTS JESD204C TX and RX IP
1. About the GTS JESD204C Intel® FPGA IP Design Example User Guide
2. GTS JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204C Design Example
4. Document Revision History for the GTS JESD204C Intel® FPGA IP Design Example User Guide

2.3.2. Directory Structure

The GTS JESD204C design example directories contain generated files for the design examples.
Figure 3. Directory Structure for GTS JESD204C Agilex™ 5 Design Example
Table 6.  Directory Files
Folders Files
ed/rtl
  • <data_path>
    • j204c_gts_<data_path>_ip.qsys
    • j204c_gts_<data_path>_ss.qsys
    • altera_s10_user_rst_clkgate_0.ip
    • jesd204c_gts_se_outbuf_1bit.ip
simulation/models
  • tb_top.sv
simulation/mentor
  • modelsim_sim.tcl
  • tb_top_waveform.do
simulation/synopsys
  • vcs
    • vcs_sim.sh
    • tb_top_wave_ed.do
  • vcsmx
    • vcsmx_sim.sh
    • tb_top_wave_ed.do
simulation/setup_scripts/common
  • modelsim_files.tcl
  • vcs_files.tcl
  • vcsmx_files.tcl
  • xcelium_files.tcl
simulation/setup_scripts/mentor
  • msim_setup.tcl
simulation/setup_scripts/synopsys
  • vcs
    • vcs_setup.sh
  • vcsmx
    • vcsmx_setup.sh
    • synopsys_sim.setup
Level Two Title