GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 813973
Date 8/14/2025
Public

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Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for GTS Serial Lite IV Design Example 4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for GTS Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Analog Parameters
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for GTS Serial Lite IV Design Example
4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2025.08.14 25.1.1 8.0.0
  • Updated sections:
    • About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
    • Design Example Block Diagram
    • Hardware and Software Requirements
    • Design Example Parameters
    • Directory Structure
    • Simulation
2025.03.07 24.3.1 6.0.0
  • Updated sections:
    • Hardware and Software Requirements
    • Compiling and Testing the Design
    • Detailed Description for GTS Serial Lite IV Design Example
    • Features
    • Analog Parameters
  • Added figures:
    • PMA Settings with RX Auto Adaptation Mode
    • PMA Settings with RX Manual Adaptation Mode
  • Updated Directory Structure for Agilex™ 5 GTS Serial Lite IV Design Example figure
2024.08.05 24.2 4.0.0
Added sections:
  • Compiling and Testing the Design
  • Simulation Results for Basic Mode
  • Simulation Result for Full Mode
  • Hardware Testing
  • Analog Parameters
Updated sections:
  • Hardware and Software Requirements
  • Design Example Parameters
  • Directory Structure
2024.04.01 24.1 3.0.0 Initial release.
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