MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 3/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Design 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. MIPI CSI-2 Design Components 2.4.2. MIPI CSI-2 IP Design Example Reset Scheme 2.4.3. MIPI CSI-2 IP Design Example Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Plotting Waveforms 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. PHY-Protocol Interface (PPI) Loopback 2.5.5.3. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

1.1. Generating the Design

Use the MIPI CSI-2 Intel® FPGA IP parameter editor in the Quartus® Prime software to generate the design example.
Figure 2. Design Example Tab
  1. Select Tools > IP Catalog and select Agilex™ 5 as the target device family.
    Note: The design example only supports Agilex™ 5 devices.
    The IP parameter editor appears.
  2. In the IP Catalog, locate and double-click MIPI CSI-2 Intel FPGA IP.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip/<your_ip>.qsys.. Click OK.
    The IP parameter editor appears.
  4. In the Design Example tab, turn on Synthesis and or Simulation to generate the design example.
    Note: The MIPI CSI-2 RX-only design does not support simulation.
    1. If you turn on Simulation, you can select Full simulation or Fast simulation

    Full simulation simulates the CSI-2 TX and RX IPs including D-PHY TX and RX in the loopback. Fast simulation bypasses the D-PHY IP and performs loopback at the PPI between the CSI-2 TX and CSI-2 RX IPs directly. Fast simulation reduces simulation time

  5. Under Generate File Format, select Verilog or VHDL.
  6. Under Target Development Kit, No development kit is set by default and the Target Device is set to Agilex™ 5 devices. The default device OPN is automatically selected based on the target device of the project to match the device on this development kit.
  7. Click the Generate Example Design button to generate the project files.

Section Content
Design Example Parameters

Level Two Title