MIPI CSI-2 Intel® FPGA IP Design Example User Guide

ID 813931
Date 3/30/2025
Public

2.5.6. Known Limitations

The MIPI CSI-2 IP Design Example has the following known limitations:
  • Xcelium is not supported.
  • Aldec Riviera-PRO is only supported for fast Simulations.
  • Passthrough mode simulation is only supported in loopback fast simulations.
  • Passthrough mode is not supported for 8-lane configurations in A5E 005B devices because of insufficient memory resources.
  • The B18A package provides a limited number of lanes for D-PHY interfaces, with available bonded pins between BYTE4 to BYTE7. Conflicts may arise between the RZQ pin and data lane pins. For placement rules, refer to MIPI D-PHY User Guide
  • YUV420 has limited support for 4-D-PHY and 8-D-PHY lanes (1C & 4D and 1C & 8D). Full simulation does not support 8-D-PHY lanes