Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813899
Date 8/04/2025
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Document Table of Contents
Document Table of Contents x
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) 3. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (GTS) with IEEE 1588v2 4. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII TBI PCS and Embedded PMA Signals (LVDS I/O) with IEEE 1588v2 5. Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 6. Document Revision History for the Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components 1.2.3.2. Clock Signals
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Design Example Testbench 2.1.4. Compiling the Design Example
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Interface Signals
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clock Signals
2.2.4. Simulation x
2.2.4.1. Testbench
3. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (GTS) with IEEE 1588v2 x
3.1. Quick Start Guide 3.2. Design Example Description
3.1. Quick Start Guide x
3.1.1. Directory Structure 3.1.2. Generating the Design Example 3.1.3. Simulating the Design Example Testbench 3.1.4. Compiling the Design Example in Hardware
3.1.2. Generating the Design Example x
3.1.2.1. Design Example Parameters
3.2. Design Example Description x
3.2.1. Features 3.2.2. Hardware and Software Requirements 3.2.3. Functional Description 3.2.4. Simulation 3.2.5. Hardware Testing 3.2.6. Interface Signals
3.2.3. Functional Description x
3.2.3.1. Design Components 3.2.3.2. Clock Signals
3.2.4. Simulation x
3.2.4.1. Testbench
3.2.5. Hardware Testing x
3.2.5.1. Test Procedure
4. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII TBI PCS and Embedded PMA Signals (LVDS I/O) with IEEE 1588v2 x
4.1. Quick Start Guide 4.2. Design Example Description
4.1. Quick Start Guide x
4.1.1. Directory Structure 4.1.2. Generating the Design Example 4.1.3. Simulating the Design Example Testbench 4.1.4. Compiling the Design Example
4.1.2. Generating the Design Example x
4.1.2.1. Design Example Parameters
4.2. Design Example Description x
4.2.1. Features 4.2.2. Hardware and Software Requirements 4.2.3. Functional Description 4.2.4. Simulation 4.2.5. Interface Signals
4.2.3. Functional Description x
4.2.3.1. Design Components 4.2.3.2. Clock Signals
4.2.4. Simulation x
4.2.4.1. Testbench
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS)
3. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (GTS) with IEEE 1588v2
4. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII TBI PCS and Embedded PMA Signals (LVDS I/O) with IEEE 1588v2
5. Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
6. Document Revision History for the Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

4.1.2. Generating the Design Example

Figure 28. Procedure to Generate Design Example
Figure 29. Example Design Tab in the Triple-Speed Ethernet IP Parameter Editor

Follow these steps to generate the hardware design example and testbench:

  1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
  2. Select Agilex™ 3 or Agilex™ 5 device family and select a device for your design.
  3. Click Finish to close the wizard.
  4. In the IP Catalog, locate and select Interface Protocol > Ethernet > 1G Multi-rate Ethernet > Triple-Speed Ethernet IP. The New IP Variation window appears.
  5. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  6. Click OK. The parameter editors appears.
  7. To generate a design example, select a Multi channel Triple Speed Ethernet MAC PCS Example Design (LVDS) with 1588 ( Agilex™ 5, Agilex™ 3) preset from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design. The parameter editor automatically sets the parameters required to generate the design example.
    1. To generate a single channel design, navigate to the Core Configuration tab in the parameter editor and set the Number of Ports to 1.
    2. To generate a multi channel design, navigate to the Core Configuration tab in the parameter editor and set the Number of Ports to 4 (default).
  8. For Example Design Files, select the Simulation option to generate the testbench, or the Synthesis option to generate the hardware design example.
    Note: You must select at least one of the options to generate the design example.
  9. On the Example Design tab, under Generated HDL Format, select Verilog or VHDL.
    Note: If you select VHDL, you must simulate the testbench with a mixed language simulator. The device under test is a VHDL model, but the main testbench file is a System Verilog file.
  10. Under Target Development Kit, select None.
  11. Click the Example Design: “example_design” button. The Select Example Design Directory window appears.
  12. If you want to modify the design example directory path or name from the defaults displayed (intel_eth_tse_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).
    Note: You must perform the parameter settings based on the steps above to generate the design example.
  13. Click OK.

Section Content
Design Example Parameters

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