Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex 3™ and Agilex™ 5 FPGAs and SoCs
ID
813899
Date
4/07/2025
Public
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1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS)
3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
2.2.1. Features
- Generates the design example for Triple-Speed Ethernet Multiport Ethernet MAC without Internal FIFO and PCS with LVDS I/O using multi-channel shared FIFO.
- TX and RX serial loopback mode (In simulation).
- Supports only 4 ports.
- Supports packet statistics report on both MAC transmitter and MAC receiver.
- Supports system console user interface. You can make use of the TCL-based user interface to dynamically configure and monitor any registers in this design example.
- Basic packet checking capabilities of traffic monitor.