Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex 3™ and Agilex™ 5 FPGAs and SoCs

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ID 813899
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) 3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Design Example Testbench 2.1.4. Compiling the Design Example
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Interface Signals
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clock and Reset Signals
2.2.4. Simulation x
2.2.4.1. Testbench
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS)
3. Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

1.1.2.1. Design Example Parameters

Table 3.  Parameters in the Example Design Tab
Parameter Description
Select Design Available example designs for the IP parameter settings.
Example Design Files

The files to generate for the different development phase.

  • Simulation—generates the necessary files for simulating the example design.
  • Synthesis—generates the synthesis files. Use these files to compile the design in the Quartus® Prime Pro Edition software for hardware testing and perform static timing analysis.
Generate File Format The format of the RTL files for simulation—Verilog or VHDL.
Select Board Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit.

If this menu is not available, there is no supported board for the options that you select.

Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1): This option allows you to test the design example on the selected Intel® FPGA IP development kit. This option automatically selects the Target Device to match the device on the Intel® FPGA IP development kit. If your board revision has a different device grade, you can change the target device.

None: This option excludes the hardware aspects for the design example.
Note: If you are generating a design example for Agilex™ 3 device, select None as the Target Development Kit, as hardware support is currently not available.
Select Device Initialization Clock Example Designs using transceivers must provide an external clock to the OSC_CLK_1 device pin. The clock should be 25 MHz,100 MHz, or 125MHz.
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