Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813775
Date 1/23/2025
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 5 FPGAs 7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations
1.3.1. CvP Limitations x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes 2.3. Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe Wake-Up Time Requirement
4.1.2. PCIe Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 5 FPGAs
7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs

7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Changes
2025.01.23 Added reference to the Hard Processor System Booting User Guide: Agilex™ 5 SoCs in the following sections:
  • CvP Limitations
  • CvP Update Mode
2024.10.02
  • Updated the label in PCIe* Timing Sequence in CvP Initialization Mode figure to FPGA Bottom Left or Top Left Transceiver Status.
  • Corrected recommended periphery image size limit to 12 Mb in the Configuration Images section.
  • Updated row C in the Power-Up Sequence Timing in CvP Initialization Mode table.
  • Updated the FPGA Power Supplies Ramp-Up Time and POR figure in the FPGA Power Supplies Ramp Time Requirement section.
2024.04.01 Initial release.
Level Two Title