Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs
ID
813762
Date
5/09/2025
Public
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. HPS Boot Flows
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 3 and Agilex™ 5 SoC Boot Flow
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices
4.12. QSPI Controller Ownership Selection Impact on the HPS Software
6.2.2.2. Pin Location Differences
The placement of non-HPS EMIF pins in the HPS IO banks must be consistent between the two designs. It is highly recommended to constrain all non-HPS EMIF pins in the design. If not constrained, Quartus® Prime might place them optimally for one design and differently for the next, causing an IO hash mismatch. Use the Pin Planner or location assignments in the QSF file to resolve any pin location discrepancies. Below is a template for the QSF location assignment:
set_location_assignment PIN_<ID> -to <pin name>