Hard Processor System Component Reference Manual: Agilex™ 5 SoCs
ID
813752
Date
8/15/2025
Public
1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Simulating the Agilex™ 5 HPS bridges (H2F, LWH2F, F2SDRAM, F2H)
5. Design Guidelines
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
2.3.1. Configurations for HPS IP
2.3.2. Configurations for HPS EMIF IP
2.3.3. Graphical Connections of HPS to HPS-EMIF
2.3.4. Configuration when using ECC
2.3.5. Configuration of HPS EMIF Calibration Settings
2.3.6. Supported Memory Protocols Among Device Families
2.3.7. IO96 Bank and Lane Usage for HPS EMIF
2.3.8. Quartus Report of I/O Bank Usage
2.3.9. Debugging with the External Memory Interface Debug Toolkit
3.1.2. Generating the HPS Simulation Model in Platform Designer
Note: This section describes how to generate the simulation model when a single .qsys system is in the Quartus® Prime project. It does not describe the method to generate the simulation model when multiple .qsys systems are in the Quartus® Prime project. There are plans to describe this in a future version of this document.
The following steps outline how to generate the simulation model:
- In Quartus® Prime Pro Edition software, launch the Platform Designer and open your system design that has been created in the previous section.
- In Platform Designer, click on the Generate HDL button.
Figure 46. Platform Designer - Generate HDL button
- A Generation Window opens. In the Simulation section, use the Create simulation model dropdown to choose Verilog or VHDL.
- Select which of the supported simulators to generate files. (Leaving all the boxes unselected generates files for all simulators.)
Note: When selecting the Clear output directories for selected generation targets, it erases all files in the output directories including any previous setup scripts.
- Click the Generate button.
Figure 47. Platform Designer - Select Simulators to Generate