Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

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ID 813752
Date 11/10/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Agilex™ 5 Hard Processor System Component 2. Configuring the Agilex™ 5 Hard Processor System Component 3. Simulating the Agilex™ 5 HPS Component 4. Design Guidelines
1. Introduction to the Agilex™ 5 Hard Processor System Component x
1.1. Release Notes 1.2. Micro Processor Unit 1.3. Application Processor Subsystem 1.4. Peripheral Subsystem 1.5. CoreSight* Debug Components 1.6. Interconnect 1.7. FPGA Bridges 1.8. Introduction to the Agilex™ 5 Hard Processor System Component Revision History
1.1. Release Notes x
1.1.1. HPS IP 11.1.0 1.1.2. HPS IP 9.0.0 1.1.3. HPS IP 7.0.0 1.1.4. HPS IP 6.0.0 1.1.5. HPS IP 5.1.0 1.1.6. HPS IP 4.0.0
2. Configuring the Agilex™ 5 Hard Processor System Component x
2.1. Parameterizing the HPS Component 2.2. HPS-FPGA Interfaces 2.3. SDRAM 2.4. HPS Clocks, Reset, Power 2.5. I/O Delays 2.6. Pin Mux and Peripherals 2.7. Generating and Compiling the HPS Component 2.8. Using the Address Span Extender Component 2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2. HPS-FPGA Interfaces x
2.2.1. General 2.2.2. HPS FPGA Bridges 2.2.3. DMA Controller Interface 2.2.4. Interrupts
2.2.1. General x
2.2.1.1. Enable MPU Standby and Event Signals 2.2.1.2. Enable General Purpose Signals 2.2.1.3. Enable Debug APB* Interface 2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events 2.2.1.5. Enable SWJ-DP JTAG Interface 2.2.1.6. Enable FPGA Cross Trigger Interface 2.2.1.7. Enable AMBA* Trace Bus (ATB)
2.2.2. HPS FPGA Bridges x
2.2.2.1. FPGA to HPS Subordinate 2.2.2.2. FPGA to SDRAM Subordinate 2.2.2.3. HPS to FPGA Manager 2.2.2.4. Lightweight HPS to FPGA Manager
2.2.4. Interrupts x
2.2.4.1. FPGA-to-HPS 2.2.4.2. HPS-to-FPGA
2.3. SDRAM x
2.3.1. Configurations for HPS IP 2.3.2. Configurations for HPS EMIF IP 2.3.3. Graphical Connections of HPS to HPS-EMIF 2.3.4. Configuration when using ECC 2.3.5. Configuration of HPS EMIF Calibration Settings 2.3.6. Supported Memory Protocols Among Device Families 2.3.7. IO96 Bank and Lane Usage for HPS EMIF 2.3.8. Quartus Report of I/O Bank Usage 2.3.9. Debugging with the External Memory Interface Debug Toolkit
2.4. HPS Clocks, Reset, Power x
2.4.1. Input Clocks 2.4.2. PLL Clocks 2.4.3. Power and Resets
2.4.1. Input Clocks x
2.4.1.1. External Clocks 2.4.1.2. FPGA-to-HPS Clocks 2.4.1.3. Peripheral FPGA Clocks
2.4.2. PLL Clocks x
2.4.2.1. Main PLL Output 2.4.2.2. Peripheral PLL Output 2.4.2.3. MPU Clocks 2.4.2.4. NOC Clocks 2.4.2.5. Peripheral Clocks 2.4.2.6. HPS-to-FPGA User Clocks
2.4.3. Power and Resets x
2.4.3.1. Power Configurations 2.4.3.2. Reset Signals
2.6. Pin Mux and Peripherals x
2.6.1. Pin Mux GUI 2.6.2. EMAC PTP Interface 2.6.3. HPS I/O Open Drain 2.6.4. HPS I/O Locations
2.6.1. Pin Mux GUI x
2.6.1.1. Auto-Place IP 2.6.1.2. Advanced
2.6.1.1. Auto-Place IP x
2.6.1.1.1. Options for NAND, SDMMC, TRACE, TPIU, EMAC
2.6.1.1.1. Options for NAND, SDMMC, TRACE, TPIU, EMAC x
2.6.1.1.1.1. HPS IO Placement Priority
2.6.1.2. Advanced x
2.6.1.2.1. Advanced IP Placement 2.6.1.2.2. Advanced FPGA Placement
3. Simulating the Agilex™ 5 HPS Component x
3.1. Simulation Flows 3.2. Simulating the Agilex™ 5 HPS Example Design Across Bridges (H2F, LWH2F, F2SDRAM, and F2H) 3.3. Simulating the Agilex™ 5 HPS Component Revision History
3.1. Simulation Flows x
3.1.1. Setting Up the HPS Component for Simulation 3.1.2. Generating the HPS Simulation Model in Platform Designer
3.2. Simulating the Agilex™ 5 HPS Example Design Across Bridges (H2F, LWH2F, F2SDRAM, and F2H) x
3.2.1. Use Cases 3.2.2. Configuring the Interfaces 3.2.3. Implementing Example Design Callback Procedure 3.2.4. Running the Testbench
3.2.1. Use Cases x
3.2.1.1. Default Use Case 3.2.1.2. Test Array IP Use Case
3.2.4. Running the Testbench x
3.2.4.1. Questa*-Altera® FPGA Edition Example 3.2.4.2. Synopsys* VCS Example 3.2.4.3. Cadence Xcelium* Example
4. Design Guidelines x
4.1. HPS System Reset Considerations 4.2. Design Guidelines Revision History
1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Design Guidelines

3.2.2. Configuring the Interfaces

Follow these steps to set up the HPS component for simulation.
  1. Open the Quartus® Prime software from the desired location. This example uses <path>/EXAMPLE/.
  2. Click File > New Project Wizard to create a project and populate it with the desired device and the required parameters. For this example, name the project simple.
  3. Once completed, click Tools > Platform Designer within Quartus® Prime to create a new platform designer system.
    Figure 54. Open the Platform Designer system
  4. Populate the desired project name. For this example, use simple.
    Figure 55. Enter the filename for the system
  5. Click Create, and click Create again.
  6. In Platform Designer, add the HPS component from the Platform Designer Component Library to the design.
    Figure 56. Add the HPS component from Platform Designer Component Library
  7. From the Hard Processor IP parameter window, click the Example Design tab.
  8. Configure the H2F, LWH2F, F2SDRAM, and F2H bridges as shown in the following examples.
    Figure 57. Options for the Manager Interfaces
    Figure 58. Options for the Subordinate Interfaces
  9. For the file generation settings, select the necessary run scripts to run the associated testbenches. You can run the script straight out of generation.
    Note: The Riviera-PRO* option is temporarily disabled as it is currently not supported as part of the Altera ACE5-Lite BFM component.
    Figure 59. Options for generating files and scripts
  10. Click Finish.
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