Triple-Speed Ethernet IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

ID 813669
Date 8/04/2025
Public
Document Table of Contents

4.4.2. IEEE 1588v2 Features

  • Supports 4 types of PTP clock on the transmit datapath:
    • Master and slave ordinary clock
    • Master and slave boundary clock
    • End-to-end (E2E) transparent clock
    • Peer-to-peer (P2P) transparent clock
  • Supports PTP message types:
    • PTP event messages—Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp.
    • PTP general messages—Follow_Up, Delay_Resp, Pdelay_Resp_Follow_Up, Announce, Management, and Signaling.
  • Supports simultaneous 1-step and 2-step clock synchronizations on the transmit datapath.
    • 1-step clock synchronization—The MAC function inserts accurate timestamp in Sync PTP message or updates the correction field with residence time.
    • 2-step clock synchronization—The MAC function provides accurate timestamp and the related fingerprint for all PTP message.
  • Supports the following PHY operating speed accuracy:
    • random error:
      • 10Mbps—NA
      • 100Mbps—timestamp accuracy of ± 5 ns
      • 1000Mbps—timestamp accuracy of ± 2 ns
    • static error—timestamp accuracy of ± 3 ns