Triple-Speed Ethernet IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813669
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. About Triple-Speed Ethernet IP for Agilex™ 3 and Agilex™ 5 devices 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Register Space 6. Interface Signals 7. Design Considerations 8. Timing Constraints 9. Testbench 10. Triple-Speed Ethernet Debug Checklist 11. Software Programming Interface 12. Triple-Speed Ethernet IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 13. Document Revision History for the Triple-Speed Ethernet IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs A. Ethernet Frame Format B. Simulation Parameters
1. About Triple-Speed Ethernet IP for Agilex™ 3 and Agilex™ 5 devices x
1.1. Release Information 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Features 1.5. 10/100/1000 Ethernet MAC Versus Small MAC 1.6. High-Level Block Diagrams 1.7. Performance and Resource Utilization
2. Getting Started x
2.1. Introduction to Altera IP Cores 2.2. Installing and Licensing IPs 2.3. Specifying the IP Core Parameters and Options 2.4. IP Core Generation Output 2.5. Simulating IP Cores
2.2. Installing and Licensing IPs x
2.2.1. Intel FPGA IP Evaluation Mode
2.4. IP Core Generation Output x
2.4.1. Design Constraint File
3. Parameter Settings x
3.1. Core Configuration 3.2. Ethernet MAC Options 3.3. FIFO Options 3.4. Timestamp Options 3.5. PCS/Transceiver Options 3.6. Analog Parameter Settings 3.7. LVDS Pin Settings
4. Functional Description x
4.1. 10/100/1000 Ethernet MAC 4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA (GTS) 4.3. HPS GMII Adapter 4.4. Precision Time Protocol 4.5. Deterministic Latency
4.1. 10/100/1000 Ethernet MAC x
4.1.1. MAC Architecture 4.1.2. MAC Interfaces 4.1.3. MAC Transmit Datapath 4.1.4. MAC Receive Datapath 4.1.5. MAC Transmit and Receive Latencies 4.1.6. FIFO Buffer Thresholds 4.1.7. Congestion and Flow Control 4.1.8. Magic Packets 4.1.9. MAC Local Loopback 4.1.10. MAC Reset 4.1.11. PHY Management (MDIO) 4.1.12. Connecting MAC to External PHYs
4.1.3. MAC Transmit Datapath x
4.1.3.1. IP Payload Re-alignment 4.1.3.2. Address Insertion 4.1.3.3. Frame Payload Padding 4.1.3.4. CRC-32 Generation 4.1.3.5. Interpacket Gap Insertion 4.1.3.6. Collision Detection in Half-Duplex Mode
4.1.4. MAC Receive Datapath x
4.1.4.1. Preamble Processing 4.1.4.2. Collision Detection in Half-Duplex Mode 4.1.4.3. Address Checking 4.1.4.4. Frame Type Validation 4.1.4.5. Payload Pad Removal 4.1.4.6. CRC Checking 4.1.4.7. Length Checking 4.1.4.8. Frame Writing 4.1.4.9. IP Payload Alignment
4.1.4.3. Address Checking x
4.1.4.3.1. Unicast Address Checking 4.1.4.3.2. Multicast Address Resolution
4.1.6. FIFO Buffer Thresholds x
4.1.6.1. Receive Thresholds 4.1.6.2. Transmit Thresholds 4.1.6.3. Transmit FIFO Buffer Underflow
4.1.7. Congestion and Flow Control x
4.1.7.1. Remote Device Congestion 4.1.7.2. Receive FIFO Buffer and Local Device Congestion
4.1.8. Magic Packets x
4.1.8.1. Sleep Mode 4.1.8.2. Magic Packet Detection
4.1.11. PHY Management (MDIO) x
4.1.11.1. MDIO Connection 4.1.11.2. MDIO Frame Format
4.1.12. Connecting MAC to External PHYs x
4.1.12.1. Gigabit Ethernet 4.1.12.2. Programmable 10/100 Ethernet 4.1.12.3. Programmable 10/100/1000 Ethernet Operation
4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA (GTS) x
4.2.1. 1000BASE-X/SGMII PCS Architecture 4.2.2. Transmit Operation 4.2.3. Receive Operation 4.2.4. Transmit and Receive Latencies 4.2.5. GMII Converter 4.2.6. SGMII Converter 4.2.7. Auto-Negotiation 4.2.8. Ten-bit Interface 4.2.9. 1000BASE-X/SGMII PCS Reset
4.2.2. Transmit Operation x
4.2.2.1. Frame Encapsulation 4.2.2.2. 8b/10b Encoding
4.2.3. Receive Operation x
4.2.3.1. Comma Detection 4.2.3.2. 8b/10b Decoding 4.2.3.3. Frame De-encapsulation 4.2.3.4. Synchronization 4.2.3.5. Carrier Sense 4.2.3.6. Collision Detection
4.2.6. SGMII Converter x
4.2.6.1. Transmit 4.2.6.2. Receive
4.2.7. Auto-Negotiation x
4.2.7.1. 1000BASE-X Auto-Negotiation 4.2.7.2. SGMII Auto-Negotiation
4.4. Precision Time Protocol x
4.4.1. IEEE 1588v2 Supported Configurations 4.4.2. IEEE 1588v2 Features 4.4.3. IEEE 1588v2 Architecture 4.4.4. IEEE 1588v2 Transmit Datapath 4.4.5. IEEE 1588v2 Receive Datapath 4.4.6. IEEE 1588v2 Frame Format
4.4.6. IEEE 1588v2 Frame Format x
4.4.6.1. PTP Frame in IEEE 802.3 4.4.6.2. PTP Frame over UDP/IPv4 4.4.6.3. PTP Frame over UDP/IPv6
5. Configuration Register Space x
5.1. MAC Configuration Register Space 5.2. PCS Configuration Register Space 5.3. Register Initialization
5.1. MAC Configuration Register Space x
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) 5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38) 5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B) 5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7) 5.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6) 5.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3) 5.1.7. IEEE 1588v2 Feature PMA Delay
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) x
5.1.1.1. Command_Config Register (Dword Offset 0x02)
5.2. PCS Configuration Register Space x
5.2.1. Control Register (Word Offset 0x00) 5.2.2. Status Register (Word Offset 0x01) 5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) 5.2.4. An_Expansion Register (Word Offset 0x06) 5.2.5. If_Mode Register (Word Offset 0x14)
5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) x
5.2.3.1. 1000BASE-X 5.2.3.2. SGMII MAC Mode Auto Negotiation 5.2.3.3. SGMII PHY Mode Auto Negotiation
5.3. Register Initialization x
5.3.1. Triple-Speed Ethernet System with MII/GMII or RGMII 5.3.2. Triple-Speed Ethernet System with SGMII 5.3.3. Triple-Speed Ethernet System with 1000BASE-X Interface
6. Interface Signals x
6.1. Interface Signals 6.2. Timing
6.1. Interface Signals x
6.1.1. 10/100/1000 Ethernet MAC Signals 6.1.2. 10/100/1000 Multiport Ethernet MAC Signals 6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals 6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.6. 1000BASE-X/SGMII PCS Signals 6.1.7. 1000BASE-X/SGMII PCS and PMA (LVDS) Signals 6.1.8. 1000BASE-X/SGMII 2XTBI PCS Signals 6.1.9. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) Signals 6.1.10. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) Signals 6.1.11. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (GTS) with IEEE 1588v2 6.1.12. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals (LVDS) with IEEE 1588v2
6.1.1. 10/100/1000 Ethernet MAC Signals x
6.1.1.1. Clock and Reset Signals 6.1.1.2. Clock Enabler Signals 6.1.1.3. MAC Control Interface Signals 6.1.1.4. MAC Status Signals 6.1.1.5. MAC Receive Interface Signals 6.1.1.6. MAC Transmit Interface Signals 6.1.1.7. Pause and Magic Packet Signals 6.1.1.8. MII/GMII/RGMII Signals 6.1.1.9. PHY Management Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals x
6.1.2.1. Multiport MAC Clock and Reset Signals 6.1.2.2. Multiport MAC Receive Interface Signals 6.1.2.3. Multiport MAC Transmit Interface Signals 6.1.2.4. Multiport MAC Packet Classification Signals 6.1.2.5. Multiport MAC FIFO Status Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals x
6.1.3.1. TBI Interface Signals 6.1.3.2. Status LED Control Signals 6.1.3.3. SERDES Control Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals x
6.1.4.1. GMII Clock Signals 6.1.4.2. GTS Transceiver Direct PHY Signals 6.1.4.3. GTS Reset Sequencer Signals 6.1.4.4. PMA Reconfiguration Interface Signals
6.1.6. 1000BASE-X/SGMII PCS Signals x
6.1.6.1. PCS Control Interface Signals 6.1.6.2. PCS Reset Signals 6.1.6.3. MII/GMII Clocks and Clock Enablers 6.1.6.4. GMII 6.1.6.5. MII 6.1.6.6. SGMII Status Signals
6.1.8. 1000BASE-X/SGMII 2XTBI PCS Signals x
6.1.8.1. Clock Enablers 6.1.8.2. PCS Reset Signals 6.1.8.3. TBI Interface Signals
6.1.9. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) Signals x
6.1.9.1. 1.25 Gbps LVDS Serial Interface
6.1.11. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (GTS) with IEEE 1588v2 x
6.1.11.1. Deterministic Latency Clock Signals 6.1.11.2. IEEE 1588v2 RX Timestamp Signals 6.1.11.3. IEEE 1588v2 TX Timestamp Signals 6.1.11.4. IEEE 1588v2 TX Timestamp Request Signals 6.1.11.5. IEEE 1588v2 TX Insert Control Timestamp Signals 6.1.11.6. IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals
6.2. Timing x
6.2.1. Avalon Streaming Receive Interface 6.2.2. Avalon Streaming Transmit Interface 6.2.3. GMII Transmit 6.2.4. GMII Receive 6.2.5. RGMII Transmit 6.2.6. RGMII Receive 6.2.7. MII Transmit 6.2.8. MII Receive
7. Design Considerations x
7.1. Exposed Ports in the New User Interface 7.2. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA (GTS)
8. Timing Constraints x
8.1. Creating Clock Constraints 8.2. Recommended Clock Frequency
9. Testbench x
9.1. Triple-Speed Ethernet Testbench Architecture 9.2. Testbench Components 9.3. Testbench Verification 9.4. Testbench Configuration 9.5. Test Flow 9.6. Simulation Model
9.6. Simulation Model x
9.6.1. Generate the Simulation Model 9.6.2. Simulate the IP 9.6.3. Simulation Model Files
10. Triple-Speed Ethernet Debug Checklist x
10.1. Debug Checklist 10.2. Case Study
10.2. Case Study x
10.2.1. Avalon Streaming Interface 10.2.2. Statistic Counter 10.2.3. Packet Drop 10.2.4. Congestion and Flow Control 10.2.5. Loopback 10.2.6. Link Synchronization
11. Software Programming Interface x
11.1. Driver Architecture 11.2. Directory Structure 11.3. PHY Definition 11.4. Using Multiple SG-DMA Descriptors 11.5. Using Jumbo Frames 11.6. API Functions 11.7. Constants
11.6. API Functions x
11.6.1. alt_tse_mac_get_common_speed() 11.6.2. alt_tse_mac_set_common_speed() 11.6.3. alt_tse_phy_add_profile() 11.6.4. alt_tse_system_add_sys() 11.6.5. tse_mac_setMIImode() 11.6.6. tse_mac_SwReset()
A. Ethernet Frame Format x
A.1. Basic Frame Format A.2. VLAN and Stacked VLAN Frame Format A.3. Pause Frame Format
A.3. Pause Frame Format x
A.3.1. Pause Frame Generation
B. Simulation Parameters x
B.1. Functionality Configuration Parameters B.2. Test Configuration Parameters
1. About Triple-Speed Ethernet IP for Agilex™ 3 and Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Triple-Speed Ethernet Debug Checklist
11. Software Programming Interface
12. Triple-Speed Ethernet IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
13. Document Revision History for the Triple-Speed Ethernet IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters

11.7. Constants

The following lists all constants defined for the MAC registers manipulation and provides links to detailed descriptions of the registers. It also list the constants that define the MAC operating mode and timeout values.

Table 109.  Constants Mapping
Constant Value Description
ALTERA_TSE_DUPLEX_MODE_DEFAULT 1 0: Half-duplex

1:Full-duplex
ALTERA_TSE_MAC_SPEED_DEFAULT 0 0: 10 Mbps

1: 100 Mbps

2: 1000 Mbps
ALTERA_TSE_SGDMA_RX_DESC_CHAIN_SIZE 1 The number of SG-DMA descriptors required for the current operating mode.
ALTERA_CHECKLINK_TIMEOUT_THRESHOLD 1000000 The timeout value when the MAC tries to establish a link with a PHY.
ALTERA_AUTONEG_TIMEOUT_THRESHOLD 250000 The auto-negotiation timeout value.
Command_Config Register (Command_Config Register (Dword Offset 0x02))
ALTERA_TSEMAC_CMD_TX_ENA_OFST 0 Configures the TX_ENA bit.
ALTERA_TSEMAC_CMD_TX_ENA_MSK 0x1
ALTERA_TSEMAC_CMD_RX_ENA_OFST 1 Configures the RX_ENA bit.
ALTERA_TSEMAC_CMD_RX_ENA_MSK 0x2
ALTERA_TSEMAC_CMD_XON_GEN_OFST 2 Configures the XON_GEN bit.
ALTERA_TSEMAC_CMD_XON_GEN_MSK 0x4
ALTERA_TSEMAC_CMD_ETH_SPEED_OFST 3 Configures the ETH_SPEED bit.
ALTERA_TSEMAC_CMD_ETH_SPEED_MSK 0x8
ALTERA_TSEMAC_CMD_PROMIS_EN_OFST 4 Configures the PROMIS_EN bit.
ALTERA_TSEMAC_CMD_PROMIS_EN_MSK 0x10
ALTERA_TSEMAC_CMD_PAD_EN_OFST 5 Configures the PAD_EN bit.
ALTERA_TSEMAC_CMD_PAD_EN_MSK 0x20
ALTERA_TSEMAC_CMD_CRC_FWD_OFST 6 Configures the CRC_FWD bit.
ALTERA_TSEMAC_CMD_CRC_FWD_MSK 0x40
ALTERA_TSEMAC_CMD_PAUSE_FWD_OFST 7 Configures the PAUSE_FWD bit.
ALTERA_TSEMAC_CMD_PAUSE_FWD_MSK 0x80
ALTERA_TSEMAC_CMD_PAUSE_IGNORE_OFST 8 Configures the PAUSE_IGNORE bit.
ALTERA_TSEMAC_CMD_PAUSE_IGNORE_MSK 0x100
ALTERA_TSEMAC_CMD_TX_ADDR_INS_OFST 9 Configures the TX_ADDR_INS bit.
ALTERA_TSEMAC_CMD_TX_ADDR_INS_MSK 0x200
ALTERA_TSEMAC_CMD_HD_ENA_OFST 10 Configures the HD_ENA bit.
ALTERA_TSEMAC_CMD_HD_ENA_MSK 0x400
ALTERA_TSEMAC_CMD_EXCESS_COL_OFST 11 Configures the EXCESS_COL bit.
ALTERA_TSEMAC_CMD_EXCESS_COL_MSK 0x800
ALTERA_TSEMAC_CMD_LATE_COL_OFST 12 Configures the LATE_COL bit.
ALTERA_TSEMAC_CMD_LATE_COL_MSK 0x1000
ALTERA_TSEMAC_CMD_SW_RESET_OFST 13 Configures the SW_RESET bit.
ALTERA_TSEMAC_CMD_SW_RESET_MSK 0x2000
ALTERA_TSEMAC_CMD_MHASH_SEL_OFST 14 Configures the MHASH_SEL bit.
ALTERA_TSEMAC_CMD_MHASH_SEL_MSK 0x4000
ALTERA_TSEMAC_CMD_LOOPBACK_OFST 15 Configures the LOOP_ENA bit.
ALTERA_TSEMAC_CMD_LOOPBACK_MSK 0x8000
ALTERA_TSEMAC_CMD_TX_ADDR_SEL_OFST 16 Configures the TX_ADDR_SEL bits (bits 16 - 18).
ALTERA_TSEMAC_CMD_TX_ADDR_SEL_MSK 0x70000
ALTERA_TSEMAC_CMD_MAGIC_ENA_OFST 19 Configures the MAGIC_ENA bit.
ALTERA_TSEMAC_CMD_MAGIC_ENA_MSK 0x80000
ALTERA_TSEMAC_CMD_SLEEP_OFST 20 Configures the SLEEP bit.
ALTERA_TSEMAC_CMD_SLEEP_MSK 0x100000
ALTERA_TSEMAC_CMD_WAKEUP_OFST 21 Configures the WAKEUP bit.
ALTERA_TSEMAC_CMD_WAKEUP_MSK 0x200000
ALTERA_TSEMAC_CMD_XOFF_GEN_OFST 22 Configures the XOFF_GEN bit.
ALTERA_TSEMAC_CMD_XOFF_GEN_MSK 0x400000
ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_OFST 23 Configures the CNTL_FRM_ENA bit.
ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_MSK 0x800000
ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_OFST 24 Configures the NO_LENGTH_CHECK bit.
ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_MSK 0x1000000
ALTERA_TSEMAC_CMD_ENA_10_OFST 25 Configures the ENA_10 bit.
ALTERA_TSEMAC_CMD_ENA_10_MSK 0x2000000
ALTERA_TSEMAC_CMD_RX_ERR_DISC_OFST 26 Configures the RX_ERR_DISC bit.
ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK 0x4000000
ALTERA_TSEMAC_CMD_CNT_RESET_OFST 31 Configures the CNT_RESET bit.
ALTERA_TSEMAC_CMD_CNT_RESET_MSK 0x80000000
Tx_Cmd_Stat Register (Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B))
ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_OFST 17 Configures the OMIT_CRC bit.
ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_MSK 0x20000
ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_OFST 18 Configures the TX_SHIFT16 bit.
ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK 0x40000
Rx_Cmd_Stat Register (Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B))
ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_OFST 25 Configures the RX_SHIFT16 bit
ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK 0x2000000
Level Two Title