Visible to Intel only — GUID: dxi1662619108492
Ixiasoft
Visible to Intel only — GUID: dxi1662619108492
Ixiasoft
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17)
The following table lists the base registers you can use to configure the MAC function. A software reset does not reset these registers except the first two bits (TX_ENA and RX_ENA = 0) in the command_config register.
Dword Offset |
Name | R/W | Description | HW Reset |
---|---|---|---|---|
0x00 | rev | RO |
|
<IP version number> |
0x01 | scratch 8 | RW | Scratch register. Provides a memory location for you to test the device memory operation. | 0 |
0x02 | command_config | RW | MAC configuration register. Use this register to control and configure the MAC function. The MAC function starts operation as soon as the transmit and receive enable bits in this register are turned on. Therefore, Altera recommends that you configure this register last. | 0 |
0x03 | mac_0 | RW | 6-byte MAC primary address. The first four most significant bytes of the MAC address occupy mac_0 in reverse order. The last two bytes of the MAC address occupy the two least significant bytes of mac_1 in reverse order. For example, if the MAC address is 00-1C-23-17-4A-CB, the following assignments are made: mac_0 = 0x17231c00 mac_1 = 0x0000CB4a Ensure that you configure these registers with a valid MAC address if you disable the promiscuous mode (PROMIS_EN bit in command_config = 0). |
0 |
0x04 | mac_1 | RW | 0 | |
0x05 | frm_length | RW/ RO |
|
1518 |
0x06 | pause_quant | RW |
|
0 |
0x07 | rx_section_empty | RW/ RO |
Variable-length section-empty threshold of the receive FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. This threshold is typically set to (FIFO Depth – 16). Set this threshold to a value that is below the rx_almost_full threshold and above the rx_section_full or rx_almost_empty threshold. In the 10/100 Mbps and 1000 Mbps small MAC variations, this register is RO and the register is set to a fixed value of (FIFO Depth – 16). |
0 |
0x08 | rx_section_full | RW/ RO |
Variable-length section-full threshold of the receive FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. For cut-through mode, this threshold is typically set to 16. Set this threshold to a value that is above the rx_almost_empty threshold. For store-and-forward mode, set this threshold to 0. In the 10/100 Mbps and 1000 Mbps small MAC variations, this register is RO and the register is set to a fixed value of 16. |
0 |
0x09 | tx_section_empty | RW/ RO |
Variable-length section-empty threshold of the transmit FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. This threshold is typically set to (FIFO Depth – 16). Set this threshold to a value below the rx_almost_full threshold and above the rx_section_full or rx_almost_empty threshold. In the 10/100 Mbps and 1000 Mbps small MAC variations, this register is RO and the register is set to a fixed value of (FIFO Depth – 16). |
0 |
0x0A | tx_section_full | RW/ RO |
Variable-length section-full threshold of the transmit FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. For cut-through mode, this threshold is typically set to 16. Set this threshold to a value above the tx_almost_empty threshold. For store-and-forward mode, set this threshold to 0. In the 10/100 Mbps and 1000 Mbps small MAC variations, this register is RO and the register is set to a fixed value of 16. |
0 |
0x0B | rx_almost_empty | RW/ RO |
Variable-length almost-empty threshold of the receive FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8. In the 10/100 Mbps and 1000 Mbps small MAC variations, this register is RO and the register is set to a fixed value of 8. |
0 |
0x0C | rx_almost_full | RW/ RO |
Variable-length almost-full threshold of the receive FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8. In the 10/100 Mbps and 1000 Mbps small MAC variations, this register is RO and the register is set to a fixed value of 8. |
0 |
0x0D | tx_almost_empty | RW/ RO |
Variable-length almost-empty threshold of the transmit FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8. In the 10/100 Mbps and 1000 Mbps small MAC variations, this register is RO and the register is set to a fixed value of 8. |
0 |
0x0E | tx_almost_full | RW/ RO |
Variable-length almost-full threshold of the transmit FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. You must set this register to a value greater than or equal to 3. A value of 3 indicates 0 ready latency; a value of 4 indicates 1 ready latency, and so forth. Because the maximum ready latency on the Avalon® streaming interface is 8, you can only set this register to a maximum value of 11. This threshold is typically set to 3. In the 10/100 Mbps and 1000 Mbps small MAC variations, this register is RO and the register is set to a fixed value of 3. |
0 |
0x0F | mdio_addr0 | RW |
|
0 |
0x10 | mdio_addr1 | RW | 1 | |
0x11 | holdoff_quant | RW |
|
0xFFFF |
0x12 – 0x16 | Reserved | — | — | 0 |
0x17 | tx_ipg_length | RW |
|
0 |