1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

ID 813667
Date 8/04/2025
Public
Document Table of Contents

1.5. Resource Utilization

The following estimates are obtained by compiling the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 devices using the Quartus® Prime Pro Edition software.
Table 7.  Resource Utilization
Speed ALM ALUT Logic Register Memory Block (M20K)
10M/100M/1G/2.5G (with 8-bit/16-bit adapter for HPS) with DR enabled 3156 3514 4715 4
10M/100M/1G/2.5G with DR enabled 1885 2519 3074 3
1G/2.5G with DR enabled 1635 2180 2585 3
10M/100M/1G/2.5G/10G with DR enabled 2650 3589 4502 11
1G/2.5G/10G with DR enabled 2049 3244 4011 11
10M/100M/1G/2.5G/5G/10G (USXGMII) 1298 1797 2119 4
2.5G MGBASE 1766 2329 2955 3
2.5G (MGBASE) with IEEE 1588v2 3008 3797 5072 4
1G/2.5G (MGBASE) with IEEE 1588v2 3047 3929 5025 4
1G/2.5G/10G MGBASE PCS only 1718 1943 3020 9
10M/100M/1G/2.5G/5G/10G MGBASE PCS only with SGMII enabled 1977 2217 3347 9
1G/2.5G/10G (MGBASE) with IEEE 1588v2 3025 4016 5184 12
10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE 1588v2 2798 3740 5454 6