1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
ID
813667
Date
8/04/2025
Public
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY IP
5. Interface Signals
6. Configuration Registers
7. Debug Checklist
8. 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
3.2.1.1. Step 1: Generating the 1G/2.5G/5G/10G Multirate Ethernet PHY IP
3.2.1.2. Step 2: QSF settings and Dynamic Reconfiguration (DR) profile assignments
3.2.1.3. Step 3: RTL Generation using Quartus® Prime Pro Edition Tool
3.2.1.4. Step 4: Instantiate the IP top file with the GTS Dynamic Reconfiguration Controller IP
5.1. Clock Signals
5.2. Reset Signals
5.3. Serial Interface Signals
5.4. Avalon Memory-Mapped Interface Signals
5.5. XGMII Signals
5.6. GMII Signals
5.7. PHY Status Signals
5.8. Transceiver Mode and Operating Speed Signals
5.9. Transceiver Status and Reconfiguration Signals
5.10. GTS Reset Sequencer Signals
5.11. Dynamic Reconfiguration Controller Interface Signals
5.4. Avalon Memory-Mapped Interface Signals
Signal Name | Direction | Width | Description | PHY Configurations |
---|---|---|---|---|
csr_address | Input | 5, 11 | Use this bus to specify the register address to read from or write to. The width is:
|
All |
csr_read | Input | 1 | Assert this signal to request a read operation. | |
csr_readdata | Output | 16, 32 | Data read from the specified register. The data is valid only when the csr_waitrequest signal is deasserted. The width is:
|
|
csr_write | Input | 1 | Assert this signal to request a write operation. | |
csr_writedata | Input | 16, 32 | Data to be written to the specified register. The data is written only when the csr_waitrequest signal is deasserted. The width is:
|
|
csr_waitrequest | Output | 1 | When asserted, indicates that the PHY is busy and not ready to accept any read or write requests.
|