Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813654
Date 1/23/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Testing the Design Example in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
1.3. Simulating the Design Example x
1.3.1. Simulation Design Example Components
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Compile the Design Example in Hardware 1.4.2. Configure the Clocks in Hardware 1.4.3. Program the FPGA
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

1.4.3. Program the FPGA

  1. On the Tools menu, click Programmer.
  2. Click Programmer > Hardware Setup.
  3. Select a programming device.
  4. Select and add the Agilex™ 5 Premium Development Kit to which your Quartus® Prime Pro Edition session can connect.
  5. Ensure that the Mode is set to JTAG.
  6. Click Auto Detect to identify the JTAG chain on the board.
  7. Select the device and click Add File.
  8. Select the programming bitstream (.sof) file.
  9. Select the check-box Program/Configure box for the .sof file.
  10. Click Start.
    Figure 7. Programmer GUI
Level Two Title