Low Latency 40G Ethernet IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
ID
813654
Date
10/24/2025
Public
1. Quick Start Guide
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 25.3 |
| IP Version 8.0.0 |
The Agilex™ 5 Low Latency 40G Ethernet IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the Quartus® Prime IP parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
The Low Latency 40G Ethernet IP also includes a compilation-only example project that you can use to quickly estimate IP core area and timing.
Figure 1. Development Steps for the Design Example