Low Latency 40G Ethernet IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813654
Date 10/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Testing the Design Example in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
1.3. Simulating the Design Example x
1.3.1. Simulation Design Example Components
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Compile the Design Example in Hardware 1.4.2. Configure the Clocks in Hardware 1.4.3. Program the FPGA
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet IP Design Example User Guide

3. Document Revision History for the Low Latency 40G Ethernet IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2025.10.24 25.3 8.0.0
  • Updated Figure:IP Tab in the Low Latency 40G Ethernet IP Parameter Editor.
  • Updated the QSFP28 loopback module in the Hardware and Software Requirements section.
  • Removed OSC component in Figure: Low Latency 40G Ethernet IP Design Example Block Diagram.
  • Added Enable Clkrx refclk recovery logic and Enable PHY Debug Master Endpoint configuration in the Design Components table.
  • Removed Device Family and Enable JTAG to Avalon® Master Bridge configuration in the Design Components table.
  • Made editorial changes throughout the document.
2025.01.23 24.3.1 5.0.0
  • Added steps to simulate the testbench using Riviera-PRO* simulator in Simulating the Design Example and Simulation Design Example Components sections.
  • Updated the instructions in Compiling and Configuring the Design Example in Hardware section.
  • Removed Generating the Design Example Using the Command-Line Interface (CLI) topic.
  • Added Example Design Tab figure in Design Example Parameters section.
  • Updated the following figures:
    • Development Steps for the Design Example
    • Example Design Tab in the Low Latency 40G Ethernet IP Parameter Editor
2024.08.16 24.2 3.0.0
  • Updated the instructions in Compiling and Configuring the Design Example in Hardware section.
  • Updated the instructions in Testing the Design Example in Hardware section.
  • Added information about development kit in Hardware and Software Requirements section.
  • Updated Figure: Example Design Tab in the Low Latency 40G Ethernet IP Parameter Editor.
2024.04.01 24.1 2.1.0 Initial release.
Level Two Title