Low Latency 40G Ethernet IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813654
Date 10/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Testing the Design Example in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
1.3. Simulating the Design Example x
1.3.1. Simulation Design Example Components
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Compile the Design Example in Hardware 1.4.2. Configure the Clocks in Hardware 1.4.3. Program the FPGA
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet IP Design Example User Guide

2.3.1. Design Components

Table 4.  Design Components
Component Description
Low Latency 40G Ethernet IP

Includes the following configuration:

  • Protocol Mode: MAC, PCS, and PMA
  • Protocol speed: 40GbE
  • Ready latency: 0
  • Enable SyncE: Disabled
  • Enable Clkrx refclk recovery logic: Disabled
  • PHY reference frequency: 156.25 MHz
  • Enable TX CRC insertion: Enabled
  • Enable link fault generation: Disabled
  • Enable preamble passthrough: Disabled
  • Enable MAC stats counters: Enabled
  • Enable Strict SFD check: Disabled
  • Enable MAC flow control: Disabled
  • Number of queues in priority flow control: 1
  • Enable PHY Debug Master Endpoint: Disabled
Reset Release IP Outputs nINIT_DONE after finishing device initialization. User mode initialization can begin as soon as the nINIT_DONE signal asserts.
GTS Reset Sequencer IP Enables pma_cu_clk for the design.
GTS System PLL Clocks IP Generates the reference clock and system PLL clock.
IOPLL IP Configures the settings of the I/O PLL.
In-System Sources & Probes IP Available in all Altera FPGA device that the Quartus® Prime Pro Edition software supports.
JTAG to Avalon® Master Bridge IP Collection of pre-wired components that provide an Avalon® Master using the new JTAG channel.
Level Two Title