Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 4/14/2025
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Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX Datapath 4.4. RX Datapath 4.5. Flow Control 4.6. Link Fault Signaling Interface
4.3. TX Datapath x
4.3.1. TX MAC 4.3.2. TX PCS 4.3.3. PMA
4.3.1. TX MAC x
4.3.1.1. Preamble Insertion 4.3.1.2. Frame Padding 4.3.1.3. Inter-Packet Gap Generation and Insertion 4.3.1.4. Frame Check Sequence (CRC-32) Insertion 4.3.1.5. TX Avalon® Streaming Filter
4.4. RX Datapath x
4.4.1. RX MAC 4.4.2. RX PCS
4.4.1. RX MAC x
4.4.1.1. IP Core Preamble Processing 4.4.1.2. IP Core CRC Checking and Dynamic Forwarding 4.4.1.3. IP Core Strict SFD Checking 4.4.1.4. Length/Type Field Processing
4.4.1.4. Length/Type Field Processing x
4.4.1.4.1. Frame Type Checking 4.4.1.4.2. Length Checking
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
5. Clocking and Reset Requirements x
5.1. Clocks 5.2. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. TX PCS Interface to User Logic 6.4. RX PCS Interface to User Logic 6.5. GTS Transceivers Signals 6.6. GTS Transceiver Reconfiguration Signals 6.7. Avalon® Memory-Mapped Management Interface 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals 6.10. Clocks 6.11. Flow Control Interface 6.12. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

7.2. TX MAC Registers

Table 28.  TX MAC Registers
Addr Name Description Reset Access
0x0 TXMAC_REVID TX MAC revision ID. 0x0627 2016 RO
0x1 TXMAC_SCRATCH Scratch register available for testing. 0x0000 0000 RW
0x2 TXMAC_NAME_0 First 4 characters of module variation identifier string, "40gMACTxCSR". 0x3430 674D

RO
0x3 TXMAC_NAME_1

Next 4 characters of IP variation identifier string, "40gMACTxCSR".

 0x4143 5278

RO
0x4 TXMAC_NAME_2 Final 4 characters of IP variation identifier string, "40gMACTxCSR". 0x0043 5352

RO
0x5 LINK_FAULT

Link Fault Configuration Register. The following bits are defined:

  • Bit [0]: When asserted, the PCS generates remote fault sequence on Ethernet link, if conditions are met.
  • Bit [1]: When asserted, the IP includes Clause 66 support for the remote link fault reporting on the Ethernet link
  • Bit [2]: This bit takes effect when both link fault reporting and unidirectional are enabled (0x405 bit[1:0] = 2' b11). When the IP is in the Disable RF mode (0x405,bit[3:0] = 4'b0111), it is backward compatible. The IP transmits data, no RF.
  • Bit [3]: It takes effect when enabling link fault reporting (0x405 bit[0] = 1'b1). It has the highest priority among the configuration bits, 0x405 [3:1]. When the IP is in the Force RF mode (0x405 {bit[3], bit[0]} = 2'b11), it stops data and transmits remote fault, regardless of value in 0x405[2:1].
0xXXXX XXX1

RW
0x6 IPG_COL_REM Specifies the number of IDLE columns to be removed in every Alignment Marker period to compensate for alignment marker insertion. You can program this register to a larger value than the default value, for clock compensation. This register is not used if DIC is disabled. 0xXXXX 0004 RW
0x7 MAX_TX_SIZE_CONFIG Specifies the maximum frame length available. The supported value is 64 or larger. 0xXXXX 2580

RW
0x8 MAC_TX_CONFIG Reserved. 0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0  
0xA TX_MAC_CONTROL TX MAC Control Register. A single bit is defined:
  • Bit[1]: VLAN detection disabled. This bit is deasserted by default, implying VLAN detection is enabled.
 0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xx0x RW
Level Two Title